Method to improve silicide formation on polysilicon

Details Method to improve silicide formation on polysilicon Method to improve silicide formation on polysilicon

2001-12-19

2004-08-17

Pert, Evan (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000

Reexamination Certificate

active

06777300

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and specifically relates to formation of a gate structure.
One of the most convenient materials for integrated circuit fabrication is doped polysilicon. This is a well-understood conductive material which is (of course) chemically compatible with silicon, has very similar work function values, and tends to have good interfaces with the materials used in silicon processes. However, the resistivity of polysilicon is much less than that of most metals. This is unfortunate since, even as the size of integrated circuits shrinks, the demand for higher performance, including decreased resistance on conductive lines, increases.
It has therefore been common for many years to “clad” polysilicon lines with a metallic conductor, in order to combine the favorable interface and work function properties of polysilicon with the lowered sheet resistance which can thus be achieved. In logic integrated circuits, polysilicon gate lines commonly use a self-aligned metal silicide, such as titanium or cobalt silicide, to reduce gate resistance and gate propagation delay. (This is typically done by depositing metal overall, annealing to cause silicide formation where silicon is exposed, and then selectively removing the unreacted metal.) Further background in silicided gate structures can be found in
Silicon Processing for the VLSI Era
, Wolf et al., 1986 (see especially Volume 1, Chapter 11 on “Refractory Metals and Their Silicides in VLSI Fabrication” and Volume 2, Chapter 3 on “Contact Technology and Local Interconnects for VLSI”), which is hereby incorporated by reference.
A new problem has arisen in recent generations of technology. With the scaling of transistor dimensions, the depth of the source/drain extension diffusions (LDD or MDD) has been reduced, and the peak doping concentration of these regions (in atoms per cubic centimeter) has increased. The present inventors have realized that this creates a problem with siliciding: very heavily doped polysilicon is slower to form a silicide. The shallow high-dose implant used to form the source/drain extensions thus degrades later silicide formation, since the upper surface of the polysilicon has an extremely high dopant concentration before annealing.
Method to Improve Silicide Formation on Polysilicon
The present application discloses an innovative way to produce a silicide on a polysilicon layer. The implant (or implants) which forms the source/drain extensions gate is masked from the gate, but allowed to hit the active area. (Optionally the main source/drain implants can also be masked from the gate.) Preferably this is done by a masking layer (e.g. silicon nitride) which is selectively removed before the metal for the salicide reaction is deposited.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
implanted ions do not reach the polysilicon surface, allowing more uniform silicide formation;
capability to selectively block the implantation into the source/drain and/or the source/drain extensions.


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