NROM fabrication method

Details NROM fabrication method NROM fabrication method

2001-10-01

2004-10-12

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S954000

Reexamination Certificate

active

06803279

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods of fabrication of nitride read only memory (NROM) cells and arrays.
BACKGROUND OF THE INVENTION
FIG. 1
, to which reference is made, illustrates a typical prior art NROM cell. This cell includes a substrate
10
in which are implanted a source
12
and a drain
14
and on top of which lies an oxide-nitride-oxide (ONO) structure
16
having a layer of nitride
17
sandwiched between two oxide layers
18
and
20
. On top of the ONO structure
16
lies a gate conductor
22
. Between source
12
and drain
14
is a channel
15
formed under ONO structure
16
.
Nitride section
17
provides the charge retention mechanism for programming the memory cell. Specifically, when programming voltages are provided to source
12
, drain
14
and gate conductor
22
, electrons flow towards drain
14
. According to the hot electron injection phenomenon, some hot electrons penetrate rough the lower section of silicon oxide
18
, especially if section
18
is thin, and are then collected in nitride section
17
. As is known in the art, nitride section
17
retains the received charge, labeled
24
, in a concentrated area adjacent drain
14
. Concentrated charge
24
significantly raises the threshold of the portion of the channel of the memory cell under charge
24
to be higher than the threshold of the remaining portion of the channel
15
.
When concentrated charge
24
is present (i.e. the cell is programmed), the raised threshold of the cell does not pert the cell to be placed into a conductive state during reading of the cell. If concentrated charge
24
is not present, the read voltage on gate conductor
22
can overcome the much lower threshold and accordingly, channel
15
becomes inverted and hence, conductive.
U.S. application Ser. No. 08/861,430 filed Jul. 23, 1996 and owned by the common inventor of the present invention describes an improved NROM cell, which is programmed in one direction and read in the reverse direction.
It is noted that the threshold voltage Vth of NROM cells is generally very sensitive to the voltages Vdrain and Vgate provided on the drain
14
and on the gate
22
, respectively. Furthermore, U.S. application Ser. No. 08/861,430 selects the voltages Vdrain and Vgate are selected in order to ensure that the charge trapped in a portion of the nitride layer
17
remains localized in that portion.
Read only memory cells, including a nitride layer in the gate dielectric (NROM) are described, inter alia, in U.S. Pat. No. 5,168,334 to Mitchell et al. and U.S. Pat. No. 4,173,766 to Hayes.
Mitchell et al. describe two processes to produce the NROM cells. In the first process, bit lines are first created in the substrate, after which the surface is oxidized. Following the oxidation, the ONO layers are added over the entire array. Polysilicon word lines are then deposited in rows over the ONO layers. Unfortunately, when an oxide layer is grown (typically under high temperature), the already present bit lines will diffuse to the side, an undesirable occurrence which limits the extent to which the cell size can be shrunk.
In the second process, the ONO layers are formed over the entire array first, on top of which conducive blocks of polysilicon are formed. The bit lines are implanted between the blocks of polysilicon after which the ONO layers are etched away from on top of the bit lines. Planarized oxide is ten deposited between the polysilicon blocks after which polysilicon word lines are deposited. Mitchell et al. utilize a planarized oxide since such can be deposited rather than grown. Mitchell et al. cannot grow an oxide over the bit lines since such an oxidation operation would also grow oxide over the polysilicon blocks and the latter must be left with a very clean surface in order to connect with the polysilicon word lines. Unfortunately, planarized oxide is not a clean oxide nor does it seal around the edges of the ONO sections Furthermore, the plied oxide adds complexity and cost to the process.
Hayes et al. describe au NROM cell having only an oxide-nitride (ON) layer. The cells in the array are created by forming layers of oxide, nitride and polysilicon (the latter to produce the gate) one after another and then patterning and etching these layers to form the on cells. The uncapped nitride in each cell does not hold charge well in both the vertical and lateral directions. Due to hole and hot electron conduction within the nitride, the charge to be stored will flow vertically towards the gate coveting it unless the nitride is tick and will flow laterally in the nitride in response to lateral electric fields.
SUMMARY OF THE PRESENT INVENTION
It is an object of the present invention to provide a method of fabricating NROM cells and NROM cell arrays with improved data retention.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge in the nitride layer. The method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the nitride layer.
Alternatively, in accordance with a preferred embodiment of the present invention, the method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer, oxidizing a portion of a top oxide layer thereby causing oxygen to be introduced into the nitride layer aid doting a remaining portion of the top oxide layer, thereby assist in controlling the amount of oxygen introduced into the nitride layer.
Further, in accordance with a preferred embodiment of the present invention, the method includes the steps of for a bottom oxide layer on a substrate, depositing a nitride layer, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby can oxygen to be introduced into the nitride layer.
There is provided, in accordance with a preferred embodiment of the present invention, a method for improving the charge retention in a nitride layer of a memory chip. The method includes the steps of deposit a nitride layer and introducing oxygen into the nitride layer.
Alternatively, in accordance with a preferred embodiment of the present invention, the method includes the steps of depositing a nitride layer, controlling the thickness of the deposited nitride layer and introducing oxygen into the nitride layer.
Further, in accordance with a preferred embodiment of the present invention, the method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer at a thickness approximate to the final thickness after fabrication, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby assisting in controlling the introduction of oxygen into the nitride layer.


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