Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-12-05
2004-08-31
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S257000, C438S264000, C438S591000, C438S593000, C257S239000, C257S261000, C257S298000, C257S315000
Reexamination Certificate
active
06784041
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-075511, filed Mar. 16, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation region and a transistor, and a method of manufacturing the semiconductor device, and particularly relates to a semiconductor device in which a contact is formed in the vicinity of the element isolation region and the transistor and the method of manufacturing the semiconductor device.
2. Description of the Related Art
Conventionally, as for a semiconductor memory, an EEPROM (Electrically Erasable Programmable Read-Only Memory) in which data is electrically written/erased is known. In the EEPROM, a memory cell is arranged respectively at the intersection where a row line and a column line are crossed each other to form a memory array. Generally, a MOS transistor having a laminated gate structure in which a floating gate and a control gate are laminated is employed for a memory cell.
As a method suitable for a memory having a large capacity among EEPROMs, a NAND type EEPROM as shown in
FIG. 33
is known. Here,
FIG. 31
is a view showing a cross section taken along the line XXXI—XXXI in
FIG. 33
, and
FIG. 32
is a view showing a cross section taken along the line XXXII—XXXII in FIG.
33
.
As shown in
FIGS. 31 and 32
, a plurality of memory cell transistors are connected in series in a memory cell array of a NAND type EEPROM, and a drain side selecting gate transistor
53
is connected to its one side, and a source side selecting gate transistor
54
is connected to the other side. A well
51
is formed on part of a semiconductor substrate
50
, and a plurality of element regions
55
in a stripe shape are formed therein. Each element region
55
is Isolated by an element isolation region
56
. On each element region
55
, a plurality of cell transistors having a laminated gate structure are formed in a line along the extension direction of the stripe, and a plurality of cell transistors are arranged in a matrix shape on the entire surface of the plural element regions
55
.
As shown in
FIG. 31
, each memory cell has a gate electrode portion
52
formed on a gate insulating film
57
located on the element region
55
, and the gate electrode section
52
is configured by laminating a floating gate electrode
58
which becomes an electric charge accumulation layer, an inter-gate insulating film
59
, a control gate electrode
60
and a gate protection film
71
. Furthermore, the control gate electrode
60
becomes, as shown in
FIG. 33
, a word line
61
by being shared with the other gate electrodes in the row direction.
In each element region, a source and a drain of each memory cell are connected with each other via a source/drain diffusion layer region
62
. In each element region, a source and a drain of each memory cell are a common region with a drain and a source of the adjacent memory cell, thereby connecting a plurality of memory cells in series to form one NAND cell memory cell unit) in each element region.
The drain side selecting gate transistor
53
and the source side selecting gate transistor
54
are connected, respectively, to one end and the other end in the direction of a bit line of each NAND cell (i.e., extension direction of stripe). The respective selecting gate transistors
53
and
54
have a gate electrode formed on the gate insulating film
57
, and connected to the NAND cell via the diffusion layer region
62
. Moreover, the selecting gate transistors
53
and
54
are configured so as to be capable of applying a potential to the floating gate electrode. The selecting gate transistors
53
functions in the same manner as a general MOSFET, and its laminated layer gate structure is similar to that of the memory cell transistor.
Moreover, a bit line contact diffusion layer
62
is formed on the side of the drain side selecting gate transistor
53
opposing to the NAND cell within the element region
55
. A bit line contact
63
is connected to this bit line contact diffusion layer
62
. This bit contact
63
is connected to a bit line
64
.
A post-oxidation film
65
is formed on the surfaces of the respective gates
52
,
53
and
54
. Then, a silicon nitride film
67
is formed On the surface of the post-oxidation film
65
, the source/drain diffusion layer
62
, the drain contact diffusion layer
62
, and a source diffusion layer
66
of the source side selecting gate
54
, that is, on the diffusion layer
66
opposite to the memory cell. An interlayer insulating film
68
is formed on the surface of the silicon nitride film
67
and further the surface thereof is flattened.
Here, the bit line contact
63
is formed in the gate insulating film
57
, the silicon nitride film
67
and the interlayer insulating film
68
. The bit line
64
is formed on the interlayer insulating film
68
. The bit line
64
is independently formed in each NAND cell formed in parallel with each other in the direction of the column (i.e., extension direction of stripe).
Moreover, a source line (not shown) is connected to the source diffusion layer
66
formed on the side of the source side selecting gate transistor opposing to the NAND cell. The source line is formed on the upper layer above the gate electrode, the contact is connected to a layer portion (not shown) to which one end of the floating gate is extended. The source line is formed commonly in a NAND cell formed in parallel in the direction of the column.
As shown in the cross sectional view shown in FIG,
32
, the plural element isolation regions
56
define the plurality of element regions
55
in the well
51
on the semiconductor substrate
50
. The bit line contact
63
is connected to the entire surface of the element regions
55
defined by the element isolation regions
56
. The silicon nitride film
67
is formed on the element isolation region
56
, and the interlayer insulating film
68
is formed thereon. The bit line contact is formed in the interlayer insulating film
68
and the silicon nitride film
67
. The bit line wiring
64
is formed on the bit line contact
68
.
Next, a method of manufacturing a conventional semiconductor device shown in FIG.
31
through
FIG. 33
will be described below with reference to FIG.
34
through FIG,
36
.
First, as shown in
FIG. 34
, the element region
55
surrounded by an element isolation region (not shown) is formed on the semiconductor substrate
50
made of silicon, the gate insulating film
57
, the floating gate electrode film layer
58
and an inter-gate insulating film layer
59
are formed thereon, and the control gate electrode layer
60
and the gate protection film layer
70
are deposited thereon. Subsequently, the memory cell gate
52
and the selecting gates
53
and
54
are formed by patterning these layers using a lithography method and etching them.
Next, the post-oxidization is performed and the post-oxidization film
65
is formed around the gate electrode of the laminated structure.
Then, the source/drain diffusion layer
62
, the drain contact diffusion layer
62
and the source diffusion layer
66
are formed by performing the ion implantation of an impurity.
After that, as shown in
FIG. 35
, for example, the silicon nitride film
67
on the order of 40 nm in thickness, for example, is deposited. At this time, the silicon nitride film
67
is formed so as to also cover the gate electrode sidewall.
Furthermore, the interlayer insulating film
68
is deposited until it is embedded between the gate electrodes, and subsequently, the interlayer insulating film
68
is flattened by performing the re-flowing using a CMP (Chemical Mechanical Polishing) and a thermal processing.
Next, as shown in
FIG. 36
, a contact hole
71
for contact with the bit line contact diffusion layer
62
adjacent to the drain side selecting gate
53
is formed in the interla
Goda Akira
Ichige Masayuki
Takeuchi Yuji
Huynh Andy
Kabushiki Kaisha Toshiba
Nelms David
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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