Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2002-06-11
2004-02-10
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S710000
Reexamination Certificate
active
06691247
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to electronic circuits and more particularly to a circuit and method for allowing testing of a memory array with a repair solution disabled. For some embodiments of the invention, this entails allowing data access to a dormant memory cell. For example, a memory cell is dormant if it is a matrix memory cell that is replaced with a redundant memory cell, or if it is a redundant memory cell that, after repair of the matrix array, is unused.
BACKGROUND OF THE INVENTION
For integrated circuits that include a memory array, the matrix memory cells are usually tested and, if necessary, repaired before the circuits are shipped to customers. If a matrix cell is found to be defective, it is replaced with a redundant memory cell. Specifically, an address decoder is programmed to map the redundant cell to the address of the defective matrix cell and to disable data access to the defective cell. Therefore, when an external circuit reads data from or writes data to this address, the address decoder deactivates the defective matrix cell, activates the redundant cell, and reroutes the data from (read) or to (write) the redundant cell. The rerouting and disabling program executed by the address decoder is often called the repair solution for the matrix array. Furthermore, for layout and circuit simplicity, many address decoders are designed to replace the entire matrix row or column containing the defective matrix cell with a redundant row or column, respectively.
One problem is that after such testing and repair of the matrix array, the redundant array often cannot be tested, and the matrix array often cannot be tested without implementing the repair solution. Such “back-end” tests (i.e., tests performed after repair of the matrix array) require a tester that has the capability to determine and store the addresses of the defective matrix cells during matrix-array testing and the unused redundant cells during redundant-array testing and to ignore errors that occur when these dormant cells are accessed. Unfortunately, due to its high cost, such a tester is usually reserved for the initial testing and repair described above, and a much cheaper back-end tester is used to test the matrix array after repair. Although such a back-end tester can test the matrix array with the repair solution enabled, it typically cannot test the matrix array with the repair solution disabled, or test the redundant array after the matrix array has been repaired. Therefore, such back-end testing of the matrix and redundant arrays is rarely, if ever performed.
One reason for testing the matrix array with the repair solution disabled is discussed with reference to
FIG. 1
, which is a schematic diagram of a portion of a Dynamic Random Access Memory (DRAM) array
10
. The array
10
includes a matrix array
11
having rows R
0
-R
N
of matrix cells
12
and a redundant array
13
having redundant rows RR
0
-RR
N
of redundant cells
14
. The matrix and redundant arrays
11
and
13
share common digit lines D and {overscore (D)}, which are coupled to a sense amplifier
15
. Furthermore, the array
10
incorporates a folded-digit-line architecture such that the cells
12
and
14
in the even rows (R
0
, R
2
, . . . , RR
0
) are coupled to the digit line D and the cells
12
and
14
in the odd rows (R
1
, R
3
, . . . , RR
N
) are coupled to the complimentary digit line {overscore (D)}.
During voltage-stress tests of the array
10
, a tester drives known logic levels onto the digit lines D and {overscore (D)} at appropriate times so as to stress the cells
12
and
14
in a desired manner. Thus, the testing apparatus must calculate the appropriate logic levels with which to drive the external data pins (not shown in
FIG. 1
) of the array
10
so as to place the desired logic levels on the digit lines D and {overscore (D)}. The relationship between the external logic levels and digit-line logic levels is referred to as the data topology of the array
10
, which is often abbreviated as the “data topo.” Likewise, the testing apparatus must calculate the respective addresses that fire the row lines R and RR. The relationship between the addresses and the row lines is called the address topology, which is often abbreviated as the “address topo.” Before the initial testing of the array
10
, the testing apparatus is programmed with the array's address and data topo equations so that it can test the array
10
and determine if any of the matrix cells
12
or redundant cells
14
are defective. For example, suppose the tester must drive a logic 1 onto an external data pin to force the sense amplifier
15
to drive a logic 1 onto line D and a logic 0 onto line {overscore (D)}. Then it follows that the tester must drive a logic 0 onto the external data pin to force the sense amplifier to drive a logic 0 onto line D and a logic 1 onto line {overscore (D)}. Likewise, if the tester reads a logic 1 from the external data pin, it determines that line D is at logic 1 and line {overscore (D)} is at logic 0, and if the tester reads a logic 0 from the external data pin, then it determines that line D is at logic 0 and line {overscore (D)} is at logic 1. Thus, these known sets of values compose parts of the data and address topos of the array
10
.
The implementation of a repair solution, however, may change the data topo, and thus for some matrix rows may change the relationship between the logic level on the external data pin and the logic levels on line D and line {overscore (D)} during such tests. When a matrix cell
12
is found to be defective, then the address decoder (not shown in
FIG. 1
) is programmed to map a redundant row RR to the address of the row R that includes the defective matrix cell
12
. For example, if a matrix cell
12
in the row R
0
is defective, then the entire row R
0
is determined to be defective, and the address decoder is programmed to replace the entire row R
0
with a redundant row RR. Because the defective matrix row R
0
is an even row, if the address decoder replaces it with an even redundant row such as RR
0
, then the redundant row will have the same data topo as the defective row, and the data topo equations can remain the same for testing the array
10
with the repair solution enabled. Conversely, if the defective row R
0
is replaced with an odd redundant row such as RR
N
, then the redundant row has a different data topo than the defective row. More specifically, suppose one wants to write logic 1 to the matrix cells
12
in the row R
0
. Then according to the data topo described above, the tester writes a logic 1 to the external data pin. If the row R
0
is replaced with row RR
0
, then the logic 1 is written to the memory cells
14
in that row as intended, and the data topo remains the same. But if the row R
0
is replaced with RR
N
, then a logic 0, not a logic 1, is written to the memory cells
14
in that row, and the data topo is different.
In addition to changing the data topo, the implementation of the repair solution may also prevent certain types of testing from being performed. For example, during a cell leakage test, the tester uses the data topo equations to write a first logic level to a cell
12
or
14
under test and a second logic level to the cells
12
or
14
adjacent to and surrounding the cell under test. (During such a test, the tester can address the array
10
as an entire array having rows R
0
-RR
N
instead of two separate arrays
11
and
13
having rows R
0
-R
N
and RR
0
-RR
N
, respectively.) Storing the opposite logic level in all of the surrounding cells creates a maximum voltage differential between these cells and the cell under test, and thus creates a worst-case leakage scenario for the cell under test. Then, the tester reads the data stored in the cell under test. If the data is equal to the first logic level, then the tester determines that the cell under test has acceptable leakage properties. But if the data is equal to the second logic level, the tester determines that the cell under test is defective
Beausoliel Robert
Bonzo Bryce P.
Dorsey & Whitney LLP
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