Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-17
2004-06-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S397000, C438S254000
Reexamination Certificate
active
06750099
ABSTRACT:
This application claims the benefit of Korean Application No. P2002-55784, filed on Sep. 13, 2002, which is hereby incorporated by reference as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor of a semiconductor device.
2. Discussion of the Related Art
A capacitor of a semiconductor device has been generally made of Oxide-Nitride-Oxide (ONO) dielectric material. However, it is recently required to make a capacitor as a material having high dielectric constant and to manufacture a semiconductor device at a low temperature so as to prevent characteristics of a logic circuit such as a transistor and a capacitor from being changed.
A method for fabricating a capacitor of a related art semiconductor device will be explained with reference to the accompanying drawings.
FIG. 1A
to
FIG. 1J
are cross-sectional views illustrating manufacturing process steps of a capacitor of a related art semiconductor device.
Referring to
FIG. 1A
, a field oxide layer
2
is formed on a semiconductor substrate
1
so as to define an active region, and gates
3
are formed on the semiconductor substrate
1
. Then, source and drain
4
are formed at both sides of each gate
3
in the semiconductor substrate
1
, and gate sidewalls
5
are formed at both sides of each gate
3
on the semiconductor substrate
1
. After forming a bit line
6
being electrically connected with the source and drain
4
, a first Inter Layer Dielectric (ILD) layer
7
is formed on an entire surface of the semiconductor substrate
1
, and is selectively removed so as to expose the source and drain
4
in a cell region, thereby defining a contact hole
8
.
As shown in
FIG. 1B
, a first doped polysilicon layer
9
is deposited on the first ILD layer
7
having the contact hole
2
, and Phosphorous Silicate Glass (PSG) is deposited on the first doped polysilicon layer
9
. Subsequently, a photoresist layer is deposited on the entire surface of the semiconductor substrate
1
, and a photoresist pattern
11
defining a capacitor region is formed in a process of selectively exposing and developing the photoresist layer. A dry-etch process is performed on the semiconductor substrate
1
using the photoresist pattern
11
as a mask, thereby forming a first doped polysilicon pattern
9
a
and a PSG pattern
10
a
, as shown in FIG.
1
C. At this time, the first doped polysilicon pattern
9
a
serves as a bottom of a capacitor lower electrode.
Referring to
FIG. 1D
, a second doped polysilicon layer
12
is deposited on the entire surface of the semiconductor substrate
1
. After that, as shown in
FIG. 1E
, the dry-etch process is performed to the second doped polysilicon layer
12
, so that a second doped polysilicon pattern
12
a
is formed. At this time, the second doped polysilicon pattern
12
a
serves as a sidewall of the capacitor lower electrode, and the first doped polysilicon pattern
9
a
and the second doped polysilicon patter
12
a
serve as the capacitor lower electrode.
As shown in
FIG. 1F
, the PSG pattern
10
a
is removed in a wet-etch process so as to open the capacitor lower electrode
9
a
and
12
a
. Next, a capacitor dielectric layer
13
having an Oxide-Nitride-Oxide (ONO) structure is formed on surfaces of the exposed capacitor lower electrode
9
a
and
12
a
, as shown in FIG.
1
G. In the capacitor dielectric layer
13
having the ONO structure, a native oxide layer, a nitride layer and an oxide layer are sequentially deposited on the surfaces of the capacitor lower electrode
9
a
and
12
a
. Then, a third doped polysilicon layer
14
is deposited on the semiconductor substrate
1
so as to form a capacitor upper electrode. The photoresist layer is deposited on the entire surface of the semiconductor substrate
1
, and then is selectively removed, so that the photoresist layer remains only on the capacitor region, thereby forming a photoresist pattern
15
. The exposed third doped polysilicon layer
14
is selectively etched by using the photoresist pattern
15
as the mask.
After removing the photoresist pattern
15
in
FIG. 1H
, a second ILD layer
16
is deposited on the entire surface of the semiconductor substrate
1
, and then is flattened. Subsequently, contact holes
17
a
and
17
b
for forming inner lines are formed so as to expose a predetermined portion of the third doped polysilicon layer
14
as the capacitor upper electrode, and predetermined portions of the semiconductor substrate
1
on a peri-region. Referring to
FIG. 1I
, the contact holes
17
a
and
17
b
for forming inner lines are buried with plug metal, thereby forming plugs
18
a
and
18
b
for inner lines. Then, metal lines
19
are formed on the plugs
18
a
and
18
b
for inner lines, as shown in FIG.
1
J.
However, the related art method for fabricating the capacitor of the semiconductor device has the following disadvantages.
During manufacturing the capacitor of the semiconductor device, defects may occur to the logic circuit (transistor, capacitor) due to complicated manufacturing process steps. To overcome this problem, it is required to form a repair circuit, so that a size of a chip increases.
Also, when the contact holes
17
a
and
17
b
are formed so as to form the plugs
18
a
and
18
b
for inner lines, a total thickness of the first and second ILD layers has to be 2000 Å or more, and each contact holes has to have different thickness, thereby complicating the dry-etch process and the burying process of the plug metal. Accordingly, a contact resistance of the plug increases.
Furthermore, the process for oxidizing the nitride layer is maintained so as to form the capacitor dielectric layer having the ONO structure at a high temperature, so that characteristic of the transistor and capacitor may be changed due to the high temperature.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a capacitor of a semiconductor device, in which it is possible to obtain reliability in an etch process, and to simplify manufacturing process steps.
Another object of the present invention is to provide a method for fabricating a capacitor of a semiconductor device, in which the capacitor of the semiconductor device is manufactured at a lower temperature, so that it is possible to prevent electrical characteristics of the semiconductor device from being changed due to a high temperature during manufacturing process steps.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a method for fabricating a capacitor of a semiconductor device includes (a) forming plugs in an insulating layer for flattening so as to be in contact with a semiconductor, on which a cell region and a peri-region are defined; (b) forming a material layer for a lower electrode on the insulating layer; (c) forming a dual mask on the material layer for the lower electrode, the dual mask having a first photoresist pattern defining a bottom of the lower electrode, and a second photoresist pattern defining a side part of the lower electrode; (d) forming capacitor lower electrodes in the same shape as the dual mask in the cell region; (e) forming a capacitor dielectric layer on the
Hynix / Semiconductor Inc.
Kennedy Jennifer M.
Morgan, Lewis & Brokius LLP
Niebling John F.
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