Testing of high speed DDR interface using single clock edge...

Details Testing of high speed DDR interface using single clock edge... Testing of high speed DDR interface using single clock edge...

2000-12-12

2004-02-10

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C365S191000, C365S233100

Reexamination Certificate

active

06691272

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data transfers across chip boundaries. More specifically, the present invention relates to testing of a high speed double data rate interface using single clock edge triggered tester data.
2. The Background Art
Over the years, since the initial development of computers, there has been a continuing drive for higher speeds. This includes both processing speeds and communication speeds. A number of devices and techniques have been developed and adopted to increase speeds. One such technique for increasing the speed of data transfers across chip boundaries has been the use of double data rate (DDR) clocking. Under this technique, data is transferred on both the positive and negative edges of a source clock. In this way, up to twice the amount of data can be transferred using the same clock speed. For example, if the clock speed is 133 MHz, then the data transfer rate is up to 266 Mega transfers per second. This is a substantial increase in speed. The DDR clocking technique has presented circuit testers with some difficulties however.
The conventional technique for testing DDR interfaces is to supply double clock edge triggered tester data. Under the 133 MHz example above, this is data at 266 MHz. Assuming that the data rate of 133 MHz is the upper limit of speed for a particular period of development, then the tester during that period is being asked to test at twice the upper limit of speed. As a result, very careful design of the test hardware is required. Further, very careful design of the test data is required The cost of this test hardware is necessarily higher then slower test hardware of the same period. These difficulties are expected to be magnified as the upper limit of speed continues to increase.
A definite need exists for a DDR testing circuit that is less complicated and expensive than that of conventional DDR testing hardware. Specifically, a need exists for a DDR testing circuit which is internally capable of generating DDR test data. Ideally, such a circuit would be robust and inexpensive. A primary purpose of the present invention is to solve these needs and to provide further, related advantages.
BRIEF DESCRIPTION OF THE INVENTION
A double data rate (DDR) circuit for testing of a high speed DDR interface using single clock edge triggered tester data is disclosed. The DDR testing circuit includes a first register, a second register, and a multiplexer (MUX). A clock signal is fed to the first register and the MUX. The inverse of the clock signal is fed to the second register. A tester data signal is fed to the first register which generates a latched tester data signal which is fed to the MUX. The inverse of the latched tester data signal is fed to the second register which generates a transformed tester data signal which is fed to the MUX. The MUX generates a combination of the latched tester data signal and the transformed tester data signal for transmission as an applied test data signal. The resulting applied test data signal has double the data rate of the tester data signal upon which it is based.


REFERENCES:
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patent: 6151664 (2000-11-01), Borkenhagen et al.
patent: 6246614 (2001-06-01), Ooishi
Dinh et al., An Approach to Testing 200ps Echo Clock to Output Timing on the Double Data Rate Synchronous Memory, 2000, IEEE, ITC International Test Conference, Paper 23.2, pp. 610-618.

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