Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-26
2004-12-07
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06828190
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 98-10584, filed on Mar. 26, 1998, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a capacitor. More particularly, the present invention relates to a method for manufacturing a capacitor having a dielectric layer with a high dielectric constant, i.e., having a high dielectric layer.
As the integration of a dynamic random access memory (DRAM) semiconductor device increases, the area that may used for a capacitor is reduced within a defined cell area. This reduction in available capacitor area makes it difficult to obtain the capacitance required for the operation of a semiconductor device using conventional dielectric layers such as an oxide layer and a nitride layer.
In order to increase capacitance, several methods have been proposed for forming a storage electrode of a capacitor using a three-dimensional structure. However, even when a three-dimensional storage electrode is used, it is still difficult to obtain the capacitances required for a highly integrated semiconductor devices using conventional dielectric layer materials.
To solve the above problems, a method has been proposed that uses a high dielectric layer, e.g., a (Ba,Sr)TiO
3
or ‘BST’ layer, for the capacitor of the semiconductor device. However, if a high dielectric layer is employed for the capacitor, a noble metal electrode must be used as the plate and storage electrodes in order to obtain a high capacitance by suppressing the reaction of the high dielectric layer with the plate and storage nodes during subsequent processes. Furthermore, the noble metal electrode has strong reaction with silicon, so a barrier layer must be formed between the noble metal electrode and the high dielectric layer. However, when this is done, the barrier layer may be oxidized during a subsequent process, which can short an electrode or increase the leakage current.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method for manufacturing a capacitor in a semiconductor device in which a barrier layer is prevented from being oxidized and the leakage current is reduced when a high dielectric layer is employed for the capacitor.
In order to achieve these objectives, a method is provided for manufacturing a capacitor of a semiconductor device, comprising: forming a storage electrode over a semiconductor substrate, forming a high dielectric layer over the storage electrode, forming a plate electrode over the high dielectric layer, performing a first post-annealing of the semiconductor substrate under an inert atmosphere at a first temperature, and performing a second post-annealing of the semiconductor substrate, after the first post-annealing, at a second temperature lower than the first temperature.
This method may further comprise forming an interdielectric layer over the plate electrode, or performing a third post-annealing, after the second post-annealing, at a third temperature lower than the second temperature.
The first and second post-annealings may be performed in sequence after forming a high dielectric layer, after forming a plate electrode, or after forming an interdielectric layer. The first and second post-annealings may also be separated, for example, the first post-annealing step being performed after forming the high dielectric layer, and the second post-annealing step being performed after forming the plate electrode.
There is also provided a method of manufacturing a capacitor of a semiconductor device in which a storage electrode, a high dielectric layer, a plate electrode and an interdielectric layer are in sequence formed on a semiconductor substrate, includes the steps of performing a first post-annealing of the semiconductor substrate under an inert atmosphere at a first temperature, e.g., about 600° C. to 900° C., after forming the high dielectric layer, the plate electrode or the interdielectric layer; and then performing a second post-annealing of the semiconductor substrate post-annealed at a second temperature lower than the first temperature, e.g., about 100° C. to 600° C.
Also, a method for manufacturing a capacitor of a semiconductor device, in which a storage electrode, a high dielectric layer, a plate electrode and an interdielectric layer are in sequence formed on a semiconductor substrate, includes the steps of: post-annealing the semiconductor substrate where the high dielectric layer is formed, under an inert atmosphere at a first temperature, e.g., 600~900° C.; and then post-annealing the semiconductor substrate post-annealed at a second temperature lower than the first temperature, e.g., 100~600° C., after forming the plate electrode.
The high dielectric layer may be formed of a dielectric material having a Perovskite such as (Sr, Ti)O
3
, (Ba, Sr)TiO
3
, Pb(Zr, Ti)O
3
, or (Pb, La)(ZrTi)O
3
. The plate electrode and the storage electrode may be formed of Pt, Ru, Ir, IrO
2
, RuO
2
, a conductive material having a Perovskite structure such as SrRuO
3
, CaSrRuO
3
, BaSrRuO
3
, an alloy containing Pt, an alloy containing Ru, or an alloy containing Ir. The post-annealing at the first and second temperatures may be performed separately or in the same location. Also, the post-annealing at the first and second temperatures may be performed in a furnace or a rapid vacuum thermal annealing apparatus.
According to a method for manufacturing a capacitor of a semiconductor device of the present invention, the first post-annealing is performed under an inert atmosphere at a high temperature after depositing a high dielectric layer, forming a plate electrode or an interdielectric layer, and then the second post-annealing is performed at a lower temperature, after the first post-annealing. The first and second post annealing steps can be performed after the deposition of the high dielectric layer, the plate electrode, or the interdielectric layer, or any combination of this, so long as the second post-annealing is performed after the first post-annealing. The two post-annealings do not have to be performed in the same place or at the same stage during the fabrication process. As a result of this process, the dielectric constant of the high dielectric layer is increased and the oxidation of a barrier layer is suppressed, which acts to reduce the leakage current.
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Wolf, S., Tauber, R. N.; Silicon Processing for the VLSI Era; Lattice Press, Sunset Beach, Ca.; 1986; pp. 57,183,388-389.*
Wolf, S.; Tauber, R. N.; Silicon Processing For the VLSI Era: vol. 1; Lattice Press; Sunset Beach, Ca.; 1986; pp. 57.*
Korean Patent Publication No. 99-165484 (Published on Jun. 26, 1997, Extracted Translation).
Lee Byoung-taek
Lee Ki-hoon
Coleman W. David
Volentine & Francos, PLLC
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