Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-04-05
2004-11-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06821845
ABSTRACT:
TECHNICAL FIELD
This invention relates to a semiconductor device containing a dielectric capacitor and a method of manufacture thereof; and, more particularly, the invention relates to a semiconductor device in which an electrode comprising Ru, RuO
2
or a mixed material of Ru and RuO
2
is deposited homogeneously on a substrate with a three-dimensional structure, and a method of manufacture thereof.
BACKGROUND OF THE INVENTION
Semiconductor memories include a DRAM (Dynamic Random Access Memory) which is capable of high speed data rewriting. Along with progress in ultra large scale integration technology, the DRAM has entered a large capacity range of 256 M to 1 G bit. Therefore, there has been a demand for integration of circuits; and, more particularly, the size of capacitors for storing information has been made finer. Means for effecting the integration of capacitors can include reduction in the film thickness of dielectrics, selection of materials of high dielectric constant and a three-dimensional structure comprising top and bottom electrodes and a dielectric.
Among these choices, for the dielectric material, it has been known that BST having a single unit cell of perovskite structure ((Ba/Sr)TiO
3
) as the crystal structure has higher dielectric constant (∈) compared with SiO
2
/Si
3
N
4
. An example of using high dielectric materials has been reported in Japan Journal of Applied Physics, 1995, 5077p (
Jpn. J. Appl. Phys.,
34, 5077, 1995). According to this report, since the condition for the aspect ratio (contact hole patterns of 800 nm depth/240 nm diameter) of a three-dimensional structure using BST is about 0.65, top and bottom electrodes and a dielectric are prepared by a sputtering method.
SUMMARY OF THE INVENTION
In the prior art described above, since Pt or Ru of the bottom electrode is prepared by the sputtering method, there is a problem in that the three-dimensional structure shows poor step coverage, and adhesion to the inside wall is small compared with that to the surface and the bottom, so that a highly three-dimensional device structure with an aspect ratio of one or more can not be attained.
This invention has been accomplished to overcome the foregoing problems and has the object of providing a semiconductor device, including a dielectric capacitor having excellent step coverage in a device structure at a high aspect ratio, along with a high integration, as well as a manufacturing method of manufacture thereof.
Heretofore, although there has been a report of preparing an electrode comprising Ru, RuO
2
or a mixture of Ru and RuO
2
thin films by a sputtering method on a three-dimensional structure with a small aspect ratio, a film forming technique using a metalorganic chemical vapor deposition process (MOCVD) has not been taken into consideration.
The present inventors have found that a homogeneous electrode comprising Ru, RuO
2
or a mixture of Ru and RuO
2
thin films can be prepared on a substrate having a three-dimensional structure within a temperature range from 180° C. or higher to 250° C. or lower by an MOCVD process using a cyclopentadienyl complex. The principle which makes it possible to prepare a homogeneous film in the temperature range described above will be explained with reference to FIG.
5
.
FIG. 5
shows a crystal structure of a ruthenium cyclopentadienyl complex used in accordance with this invention. &sgr; or &pgr; bonds are present between a 5 membered ring and ruthenium metal, and a temperature at 180° C. or higher is necessary as the energy of dissociation in view of the bonding energy. Further, the adhesion rate of the complex is constant on a Si substrate within a temperature range from 180° C. or higher and 250° C. or lower, and decomposition—adhesion on the surface proceeds preferentially at a higher temperature.
Accordingly, a film is formed only on the surface (top plane of protruded portions) in a substrate having a three-dimensional structure to form inhomogeneous films with the film thickness reduced on the inside wall and the bottom (top plane of convex portions). Particularly at a temperature higher than 300° C., island crystals are formed due to a rapid decomposing reaction to form a rough film quality for which contact can not be attained. Accordingly, a homogeneous electrode comprising Ru, RuO
2
or a mixture of Ru and RuO
2
thin films can be formed on the surface, the bottom and the inside wall on a substrate having a three-dimensional structure by the MOCVD process using a ruthenium cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.
Further, the present inventors have found that an electrode comprising Ru, RuO
2
or a mixture of Ru and RuO
2
thin films can be formed homogeneously by the MOCVD process using a &bgr;-dietone complex within a temperature range from 300° C. or higher to 500° C. or lower when a structure having a three-dimensional configuration is constituted of two insulation layers, namely, a surface layer with a small adhesion rate and a inside wall layer with a large adhesion rate. The principle will be explained with reference to FIG.
2
.
FIG. 2
shows a crystal structure of a ruthenium &bgr;-diketone complex used in accordance with this invention. &pgr; bonds are present between oxygen in a 6 membered ring and ruthenium metal and can dissociate at a temperature of 300° C. or higher in view of the bond energy. However, since dissociation of an oxygen—carbon bond or dissociation of an oxygen—ruthenium bond proceeds simultaneously. the adhesion rate is small and decomposition deposition near the surface proceeds preferentially. Further, at a temperature higher than 500° C., island crystals are formed due to violent decomposing reaction to result in a film quality that is not capable of attaining contact. Then, as shown in
FIG. 3
, a homogeneous electrode thin film comprising Ru, RuO
2
or a mixture of Ru and RuO
2
can be prepared on the surface, the bottom and the inside wall within a temperature range from 300° C. or higher to 500° C. or lower by an MOCVD process using a ruthenium &bgr;-diketone complex on a structure having a three-dimensional configuration by constituting the structure having a three-dimensional configuration with an insulation layer consisting of a dual layered structure comprising a surface layer
31
having a small adhesion rate and a side wall layer
32
having a large adhesion rate, for example, MgO/SiO
2
or Al
2
0
3
/SiO
2
for the electrode material.
This invention has been accomplished based on the studies as described above, and it features a method of manufacturing a semiconductor device by laminating to form a bottom electrode, a dielectric and a top electrode on a substrate having a three-dimensional structure, wherein a bottom electrode and a top electrode are formed by a metalorganic chemical vapor deposition method at a temperature of 180° C. or higher and 250° C. or lower using a cyclopentadienyl complex as a precursor.
The cyclopentadienyl complex is used as an Ru precursor and, more particularly, dicyclopentadienyl ruthenium is preferred. The bottom electrode and the top electrode are formed each as a thin film comprising Ru, RuO
2
or mixture of Ru and RuO
2
.
By using one Of 0
2
, H
2
, N
2
0, 0
3
, CO and CO
2
as a reaction gas, a decomposing reaction from the precursor can be promoted to form a film at a low temperature of 180° C. or higher to 250° C. or lower. Particularly, in a gas mixture of a reaction gas and a carrier gas (Ar, He or N
2
gas), the ratio of the reaction gas to the carrier gas is preferably 1% or more.
According to this feature, an electrode thin film can be prepared homogeneously on the surface, the bottom and the side wall on the substrate having a three-dimensional structure. Accordingly, it is possible to obtain a dielectric capacitor of high integration degree comprising a top electrode/a dielectric/a bottom electrode having a three-dimensional structure of high aspect ratio of 3 or more (contact hole depth/diameter).
Further, this invention has a feature in a method of ma
Fujiwara Tetsuo
Higashiyama Kazutoshi
Nabatame Toshihide
Suzuki Takaaki
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Kennedy Jennifer M.
Niebling John F.
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