Single poly-Si process for DRAM by deep N well (NW) plate

Details Single poly-Si process for DRAM by deep N well (NW) plate Single poly-Si process for DRAM by deep N well (NW) plate

2003-05-23

2004-11-30

Kang, Donghee (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S239000, C438S243000, C438S386000, C257S296000, C257S301000, C257S302000, C257S305000

Reexamination Certificate

active

06825078

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the fabrication of dynamic random access memories (DRAM's), particularly such memories in which the memory storage device is a deep trench capacitor and wherein individual memory cells are electrically isolated from each other by isolation trenches.
2. Description of the Related Art
Typical dynamic random access memories (DRAM's) consist of densely packed arrays of memory cells which are themselves comprised of a charge storage device coupled to a charge accessing device. The charge storage device is usually a capacitor and the accessing device is usually a single MOS field effect transistor (MOSFET). The transistor can be connected at its source to one plate of the storage capacitor, at its drain to a conducting bit line and at its gate electrode to a conducting word line. In a normal operation in which a 1 or a 0 is written on or read from a particular memory cell, the particular cell is selected by choosing the appropriate pair of intersecting word and bit lines. Applying a given potential to the word line turns on the access transistor and a given charge applied to the bit line will then be deposited on the capacitor plate and stored. Conversely, during reading, the word line again activates the transistor and this time the presence of the charge in the capacitor is sensed by appropriate circuitry and identified as a 1 or 0.
A major problem associated with the design of increasingly dense arrays of memory cells is the necessity of decreasing the surface area of the storage capacitors while not decreasing their capacitance. Chatterjee et al. (U.S. Pat. No. 5,208,657) describes the difficulties of using planar capacitors as storage units in a DRAM module having a 5 volt power supply. Such a capacitor would require a capacitance of approximately 50 femtofarads (fF) and, in consequence, a capacitor area of approximately 20 square microns. Not only is this area overly large for the most densely packed circuits, but it presents an unacceptably vulnerable target for alpha particles which are a causal mechanism for soft error rates (SER). Chatterjee discloses the use of a trench capacitor, which is a capacitor formed in a trench or cavity that extends vertically into the substrate of the integrated circuit that can be produced by a variety of etching mechanisms. Such capacitors gain plate area and, hence, capacitance, through an increased vertical extension rather than by horizontal extension. One plate of such a capacitor is defined by the surface of the inner wall of the doped region of the substrate within which the trench is formed. Although this inner wall forms the plate boundary, charge can in fact also be stored within a depletion region formed beneath the wall surface and extending into the doped substrate. The other plate of the capacitor, which can also be a storage plate, is a conductive core that is deposited within the trench. An oxide layer is first formed over the inner trench wall to serve as a dielectric medium and to insulate one plate from the other. The prevalence of such trench capacitors within the practice of the prior art is illustrated by the work of Kato et al. (U.S. Pat. No. 4,907,047), which teaches a method of forming a memory cell comprising a storage capacitor having a first electrode formed in the side and bottom wall portions of a primary cavity and having a second electrode formed over a dielectric film which covers said first electrode. Motonami (U.S. Pat. No. 5,185,284) describes a “groove” type capacitor (which is essentially a trench capacitor) which is circumscribed by a second capacitor to increase the overall capacitance of the combination. Cunningham (U.S. Pat. No. 6,177,697) describes a trench capacitor partially surrounded by a shallow trench isolation region (STI). The substrate is then doped through the inner surface of the trench capacitor, which is then lined with an oxide and filled with a polysilicon core to form a capacitor plate. A second capacitor plate is formed by the doped surface of the inner wall of the capacitor trench. Alsmeier et al. (U.S. Pat. No. 5,793,075) describes a deep trench capacitor within a lightly doped substrate wherein an inversion layer beneath the trench serves as one plate. Sakamoto et al. (U.S. Pat. No. 5,574,621) discloses a trench capacitor in which a plurality of conductor filled trenches connected by a conducting layer comprise a single bottom electrode and a second conducting layer, disposed over a dielectric layer, comprises a top electrode. Hoenigschmid et al. (U.S. Pat. No. 6,037,620) discloses a DRAM cell comprising a shallow isolation trench (STI), a storage trench capacitor partially overlaid by the STI and an access IGFET transistor connected to the perimeter of the capacitor by a conduction path that utilizes a buried strap interconnection.
The need to increase the density of memory cells and to integrate them with logic devices leads to complex fabrication processes. In particular, the fabrication of large DRAM arrays is complicated by a plurality of dielectric layer depositions to form gate and capacitor dielectrics and polysilicon depositions which are necessary to form the word and bit line connections to each cell and to provide connections between the access transistors and their associated storage capacitors. Even with the use of trench capacitors to reduce surface areas, the spacing between capacitors is limited by charge diffusion considerations. It is the purpose of the present invention to provide a method of isolating densely packed memory cells from each other while doing so in an efficient and cost effective manner that focuses on the minimization of dielectric and posysilicon depositions. In particular, the novel approach of forming the trench capacitor and the access transistor within a double well in which an isolation trench has already been formed provides an efficient method for forming cell plate connections having advantageous resistance properties.
SUMMARY OF THE INVENTION
A first object of this invention is to provide a method for forming one or a plurality of densely packed dynamic random access memory (DRAM) cells that can be efficiently and cost-effectively integrated with associated logic circuitry.
A second object of this invention is to provide such single or integrated DRAM cells that are characterized by low noise and soft error rates (SER).
A third object of this invention is to provide a method for forming one or a plurality of DRAM cells with high storage capacitance and low cell area.
A fourth object of this invention is to provide a method for forming DRAM cells and circuitry which can be diminished in dimension to levels exceeding that required by the 0.18 micron generation of devices and beyond.
A fifth object of this invention is to provide a method for forming such DRAM cells that produces a low cell plate connection resistance.
A sixth object of this invention is to provide a method for forming a DRAM memory cell that can be independently biased.
In accord with the objects of this invention there is provided a method for forming a single DRAM memory cell or an array of such DRAM memory cells in a semiconductor substrate. Each such cell includes a trench capacitor as a charge storage mechanism having a high capacitance and small surface area, a MOSFET as the accessing mechanism for storing and retrieving charge from the storage capacitor and a shallow isolation trench (STI) for electrically isolating one cell from another. Further in accord with the objects of this invention there is provided a method for forming the isolation trench, the capacitor and the transistor within a double well structure formed in the substrate, said well structure comprising a relatively shallow doped well of a first dopant type (the upper well) formed within a deeply implanted doped well of a second dopant type (the lower well). The isolation trench is contained within the upper well. The capacitor trench extends through the upper well and terminates within the lower well

Affiliated with

Also associated with

Rating

Single poly-Si process for DRAM by deep N well (NW) plate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single poly-Si process for DRAM by deep N well (NW) plate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single poly-Si process for DRAM by deep N well (NW) plate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3307387