Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2003-06-06
2004-11-16
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S206000, C257S207000
Reexamination Certificate
active
06818929
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a standard cell for a plurality of power supplies and technologies related thereto.
In recent years, the ever-increasing speed, integration and size of the semiconductor integrated circuits has led to the current use of a layout design using a standard cell library. On the other hand, the increased speed and integration of circuits have raised the problem of power consumption. The clock tree portion of the circuit attains large proportions of power consumption, and therefore the power consumption of the clock tree portion is required to be decreased.
As shown in
FIG. 1
, the standard cell (hereinafter sometimes referred to as the cell) of a standard cell library is configured of a power line
101
, a grounding line
102
, a transistor gate
103
, an N well
104
, a P well
105
, a P-channel diffusion region
106
and an N-channel diffusion region
107
.
In the case where two cell rows are arranged in the same direction as shown in
FIG. 2A
, all of the power lines
101
are located at the upper position, all of the grounding lines
102
are located at the lower position, and the two cell rows are separated from each other. In the case where the two cell rows are arranged in opposite directions with the power lines
101
at the central position and the grounding lines
102
at the top and bottom positions as shown in
FIG. 2B
, on the other hand, the N wells
104
of the two cell rows are in contact with each other. In this case, the two cell rows are not required to be separated from each other so that the area of the block can be reduced.
In a clock tree shown in
FIG. 3
, the clock signal is applied from a first clock buffer
202
at the center to a plurality of second clock buffers
203
radially arranged with equal distances. Further from the second clock buffers
203
, the clock signal is supplied in radial direction synchronously to a plurality of flip-flops
201
with equal distances. By reducing the source voltage of the clock tree portion below that of the logic circuit portion, the power consumption of the clock tree portion can be reduced without reducing the operating frequency of the circuit.
In the circuit configuration shown in
FIG. 4
, the only requirement for the clock tree portion
204
including the first and second clock buffers
202
,
203
is to maintain the synchronism of the clock signals. In view of this, only the clock tree portion
204
is reduced in voltage as compared with the supply potential to a circuit element string
205
including the flip-flops
201
,
201
. In this way, the power consumption for the whole circuit is reduced while securing the operating speed of the circuit element string
205
.
Presence of the cell operating at different power voltages causes the short-circuit between the power line
101
and a water. This requires separation of the circuit-element string
205
corresponding to the power voltage.
In the case where the flip-flops and the clock buffers are arranged in different rows in the block, however, the distance is lengthened between the flip-flops and the clock buffers depending on the arrangement of the flip-flops. As a result, the wiring delay is increased, thereby posing the problem that the clock signals are undesirably input to the flip-flops at different timings.
Another problem is that the cell region of the clock buffers and the cell region of the logic circuit are required to be prepared separately from each other. This poses the problem of an increased block area.
The Japanese Unexamined Patent Publication No. 10-284609 discloses a technique in which a plurality of types of power lines having different source voltages are used in the case where there coexist a plurality of types of cells having different operating voltages in the same string.
In
FIG. 5
, the cells in an even-numbered row and an odd-numbered row are arranged in opposite directions provisionally so that the N wells of adjacent rows are kept in contact with each other. Even in the case where a standard cell Un (hereinafter referred to as the single-power-supply cell) for a single power supply and a standard cell Cp for a plurality of power supplies (hereinafter referred to as the plural-power-supply cell) are adjacent to each other in a vertical direction, the N well of the single power cell Un
1
is contact with the N well of the plural-power-supply cell Cp. In view of the fact that the potential applied to the N well of the single-power-supply cell Un is different from the potential applied to the N well of the plural-power-supply cell Cp, however, a current flows and the potential of the N well of the plural-power-supply cell Cp undergoes a change. As a result, the source voltage is differentiated from the substrate voltage, so that the threshold voltage of the transistor changes and so does the operating speed thereof. In order to avoid this inconvenience, the cells in the upper row and the cells in the lower row are required to be arranged in spaced relation with each other. However, this raises the problem of an increased block area.
Also, the well is an independent entity in the cell, and the cell area is so small that a large substrate contact cannot be secured in the microprocessing, resulting in the problem that a sufficient latch-up strength cannot be obtained.
SUMMARY OF THE INVENTION
Accordingly, it is an main object of this invention to provide a technique for laying out a semiconductor integrated circuit having a plurality of source voltages without increasing the area of the block and provide a means for cutting the consumption power of the clock tree portion.
Other objects, features and advantages of the invention will be made apparent from the description below.
In order to solve the problem described above, according to a first aspect of the invention, there is provided a standard cell for a plurality of power supplies (hereinafter referred to as the plural-power-supply cell), comprising a first power line, a second power line isolated electrically from the first power line, an N well arranged in spaced relation with the whole periphery of the boundaries of the cell, a grounding line and a P well arranged in contact with the boundaries on both sides in the direction along the power lines of the cell (hereinafter sometimes referred to as the power-line direction) (FIG.
6
).
With this configuration, even in the case where standard cells (hereinafter referred to as the cells) of different source voltages are arranged on the same row, the use of the first power line and the second power line makes it possible to arrange different power lines in isolation from each other. Further, even in the case where the cells are arranged adjacently to each other in the power-line direction or the direction orthogonal thereto, the N well of a plural-power-supply cell can be isolated from the N wells of adjacent cells (FIG.
9
).
According to a second aspect of the invention, the second power line is formed in contact with the two boundaries along the power-line direction of the cell.
With this configuration, in the case where the plural-power-supply cells are arranged adjacently to each other, the first power lines and the second power lines of the cells can be connected to each other thereby to form a series of first power lines and a series of second power lines (FIG.
7
).
According to a third aspect of the invention, the N well is electrically connected to the second power line, and the P well is electrically connected to the grounding line.
With this configuration, the second power line is connected to a power supply point of a semiconductor integrated circuit and the grounding line to the grounding point of the semiconductor integrated circuit, thereby making it possible to apply the source potential to the N well and the grounding potential to the P well.
According to a fourth aspect of the invention, the N well is electrically connected to the first power line or the second power line by a wiring or a contact.
With this configuration, in the wiring step corresponding to t
Kimura Fumihiro
Matsuda Masayuki
Tsutsumi Masanori
Yano Junichi
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