Method of fabricating a patterened SOI embedded DRAM/eDRAM...

Details Method of fabricating a patterened SOI embedded DRAM/eDRAM... Method of fabricating a patterened SOI embedded DRAM/eDRAM...

2002-07-30

2004-06-15

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06750097

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor processing, and more specifically to a method of performing combined fabrication of logic and dynamic random access memory (DRAM) on the same integrated circuit.
BACKGROUND OF THE INVENTION
Conventional processes for fabricating integrated circuits having DRAM or embedded DRAM (hereinafter, eDRAM) devices therein, employ a pad silicon nitride layer (hereinafter, “pad nitride”) as a masking and polish stop layer when forming trench isolations between active devices. Using the pad nitride in such manner, shallow trench isolations (STIs) are formed in at least the supports (the logic portion of the IC) and deeper ITs (isolation trenches) may be formed for isolating vertical devices from each other in the DRAM array.
In the supports, where the active devices are “planar” (i.e., oriented parallel to the plane of the substrate, as opposed to perpendicular, i.e. “vertical”), it is undesirable for the device channel to have a sharp corner. A device corner is a location just below the gate dielectric where the device channel adjoins an isolation. At the device corner, the threshold voltage (V
T
) of the device is lowered locally due to a corner parasitic device, such that even when the device is biased at a voltage below VT, an appreciable amount of current (I
OFF
) flows through the device channel. However, when the device is turned at a voltage above V
T
, there is no meaningful increase in I
ON
, the on-current. Although it is known that the corner parasitic current can be suppressed by making the device corner less sharp; i.e. increasing its radius of curvature, achieving such result is difficult.
Sufficient corner rounding does not occur merely because a pad nitride and a thin pad silicon oxide (hereinafter referred to as “thin pad oxide”) are employed during processing, as conventionally practiced. Although some oxygen is able to diffuse through the thin pad oxide during AA oxidation (oxidation of the active areas), it does not provide sufficient AA corner rounding.
Thus, special processing must be employed for rounding the device corners of the logic devices in combined logic and DRAM chips. However, such processing is difficult and costly to integrate with presently practiced DRAM processing. For example, the device corner can be rounded by pulling back the pad nitride layer prior to active area oxidation and/or sacrificial oxidation. As practiced, pad nitride pullback is performed by isotropically etching the exposed edges of the pad nitride where they overlay the active areas in the supports. Once the corners of the active area are thus exposed, rounding can be achieved by oxidation and/or etching methods.
However, pad nitride pullback is not very desirable for use in corner rounding. During the pad nitride pullback, the DRAM array portions must be protectively masked to prevent deleterious effects, such as undercut of the trench top oxide (TTO) in the vertical device array. Thus, such corner rounding process entails costs for applying and clearing the block mask in the array. In addition, the pad nitride pullback reduces the effective width of the already narrow width array transfer device, thereby lowering the drive current of that critical device of the array.
In DRAM and chips having an embedded DRAM, it is also necessary to form bitline diffusion implants, usually via N+XA dopant implants in the array areas. Typically, in combined logic and DRAM chips, separate protective masking of the supports has been required to perform such implants in the DRAM array.
SUMMARY OF THE INVENTION
According to an aspect of the invention, a patterned silicon-on-insulator substrate method is provided of fabricating a combined integrated circuit having both a logic portion and an embedded dynamic random access memory array portion. Such method includes masking an array portion of a substrate with a first mask; implanting oxygen to form a buried oxide layer in a logic portion of the substrate not masked by the first mask; depositing and patterning a second mask over the array portion and the logic portion; and etching isolation trenches in the array portion and the logic portion, the isolation trenches defined by openings in the patterned second mask.
According to a preferred aspect of the invention, the first mask, which remains in the array portion after protecting it during the oxygen implants elsewhere, may be reused to protectively mask the array portion when rounding the device corners of the logic portion of the substrate.
According to another aspect of the invention, an integrated circuit formed on a single substrate includes at least one silicon-on-insulator (SOI) device having a rounded corner and at least one dynamic random access memory (DRAM) cell having a vertical pass gate, wherein the DRAM cell is formed on a bulk portion of the substrate.
According to another preferred aspect of the invention, a mask remaining from a corner rounding process in the logic portion of the substrate may be used to protectively mask the logic portion when performing surface implants to the array portion of the substrate.


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