Semiconductor memory device and method of repairing the same

Details Semiconductor memory device and method of repairing the same Semiconductor memory device and method of repairing the same

2002-06-04

2004-11-02

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030

Reexamination Certificate

active

06813198

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which can replace a defective memory cell with a redundant memory cell and a method of repairing the same.
2. Description of Related Art
A semiconductor memory device includes normal memory cells and redundant memory cells. When defects occur in the normal memory cells, defective memory cells are replaced with redundant memory cells in order to repair the semiconductor memory device.
However, when defective word lines are replaced with redundant word lines, only the redundant word line corresponding to the defective word lines can be used to replace the defective word lines. Therefore, when redundant memory cells connected to the redundant word lines having a decoding signal identical to the defective word lines are defective, the defective memory cells cannot be repaired.
Also, when the defective word lines are more in number than the redundant word lines corresponding to the defective word lines, the conventional semiconductor memory device cannot be repaired. Further, when the redundant word lines are associated with different decoding signals from the defective word lines, the defective word lines cannot be replaced with these redundant word lines even if these redundant word lines are not in use, thereby lowering a repairing efficiency.
SUMMARY OF THE INVENTION
The semiconductor integrated circuit according to the present invention includes a selecting circuit that selectively maps address information to rows of normal and redundant memory cells. By controlling the selecting circuit, the address information normally supplied to a row of normal or redundant row of memory cells can be supplied to a different row of normal or redundant memory cells. In one embodiment, this is accomplished by changing the parallel arrangement of row address information supplied to row decoders addressing the memory array.
By controlling the operation of the selecting circuit, a control circuit can cause a row of redundant memory cells that do not correspond to a row of normal memory cells (i.e., are associated with different decoding signals) to replace the row of normal memory cells. As a result, even if two rows of normal memory cells associated with the same decoding signal include a defective memory cell, both of the rows of memory cells can be replaced with rows of redundant memory cells. Additionally, even when a row of normal memory cells and the corresponding row of redundant memory cells both include a defective memory cell, the row of normal memory cells can be replaced with a row of redundant memory cells.


REFERENCES:
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patent: 6052318 (2000-04-01), Kirihata et al.
patent: 6118710 (2000-09-01), Tsuji
patent: 6367030 (2002-04-01), Yamauchi
patent: 6469932 (2002-10-01), Roohparvar et al.

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