Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2002-07-10
2004-06-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S723000, C257S778000, C257S781000, C257S712000, C257S717000
Reexamination Certificate
active
06756684
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages and fabrication methods thereof, and more particularly, to a FCBGA (flip-chip ball grid array) semiconductor package with a heat-dissipating device and a method for fabricating the semiconductor package.
BACKGROUND OF THE INVENTION
FCBGA (flip-chip ball grid array) semiconductor packages are an advanced packaging technology, which is characterized by implanting a plurality of solder bumps on an active surface, a surface formed with electronic components, of a chip that is electrically connected to a substrate by bonding the solder bumps to the substrate. Compared to BGA semiconductor packages, flip-chip package structure is free of forming bonding wires for chip-to-substrate electrical connection; without having to fabricate bond fingers on a substrate for wire-bonding, thereby effectively reduce the package size.
With high-integration development of semiconductor packages and chips, it becomes a critical problem to efficiently dissipate heat produced by operation of the semiconductor packages and chips.
Therefore, as shown in
FIG. 5
, U.S. Pat. No. 5,798,567 disclose a FCBGA semiconductor package
1
mounted on a circuit board
10
such as a printed circuit board (PCB). This semiconductor package
1
is provided with a chip
12
mounted on a substrate
11
in a flip-chip manner, wherein the chip
12
is implanted with a plurality of first solder bumps
13
, and electrically connected to the substrate
11
by bonding the first solder bumps
13
to the substrate
11
. A plurality of second solder bumps
14
are implanted on the substrate
11
, for allowing the semiconductor package
1
to be bonded to the circuit board
10
by means of the second solder bumps
14
, wherein a conductive adhesive
15
is applied between the chip
12
and the circuit board
10
, such that heat produced by operation of the chip
12
can be transmitted through the conductive adhesive
15
to the circuit board
10
for dissipation.
However, the above conventional semiconductor package
1
requires additional processes of surface mount technology (SMT) for applying the conductive adhesive
15
over the circuit board
10
, thereby increasing process complexity and costs in package fabrication. Moreover, in practice, the conductive adhesive
15
is a perfect heat transmission material, and therefore not capable of optimally dissipating the heat produced from the chip
12
.
Another FCBGA semiconductor package
1
′ is similar in structure to the above semiconductor package
1
, and thereby also illustrated by FIG.
5
. This semiconductor package
1
′ differs from the above semiconductor package
1
in that, a metallic heat sink
15
′ is used, instead of the conductive adhesive
15
, for connecting the chip
12
to the circuit board
10
, so as to allow the heat produced from the chip
12
to be transmitted through the heat sink
15
′ to the circuit board
10
for dissipation.
However, with the heat sink
15
′ being interposed between the chip
12
and the circuit board
10
, during a solder-reflow process for bonding the heat sink
15
′ to the circuit board
10
, the heat sink
15
′ of relatively large area would be unevenly heated, which possibly results in forming of voids or even popcorn effect, thereby adversely affect the quality of fabricated products. Moreover, due to mismatch in coefficient of thermal expansion (CTE) between the metallic heat sink
15
′ and the chip
12
, delamination may undesirably occur at interface between the heat sink
15
′ and the chip
12
, which would undesirably increase resistance of heat dissipation and degrade heat-dissipating efficiency, as well as reduced yield.
Therefore, the above drawbacks of a semiconductor package for assuring quality thereof and effectively dissipating heat produced thereby is a critical issue to solve.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a FCBGA (flip-chip ball grid array) semiconductor package with a heat-dissipating device and a method for fabricating the same, so as to effectively improve heat-dissipating efficiency of the semiconductor package.
Another objective of the present invention is to provide a FCBGA semiconductor package with a heat-dissipating device and a method for fabricating the same, without increasing process complexity of mounting the semiconductor package on a circuit board.
A further objective of the present invention is to provide a FCBGA semiconductor package with a heat-dissipating device and a method for fabricating the same, so as to prevent forming of voids or popcorn effect for the semiconductor package, thereby assuring quality of fabricated products.
A further objective of the present invention is to provide a FCBGA semiconductor package with a heat-dissipating device and a method for fabricating the same, so as to prevent delamination for the semiconductor package, thereby improving yield of fabricated products.
In accordance with the above and other objectives, the present invention proposes a FCBGA semiconductor package with a heat-dissipating device, and a method for fabricating the semiconductor package. The FCBGA semiconductor package comprises: a substrate having an upper surface and a lower surface opposed to the upper surface; at least one first chip mounted on and electrically connected to the upper surface of the substrate; at least one second chip mounted on the lower surface of the substrate in a flip chip manner, the second chip having an active surface and a non-active surface opposed to the active surface, allowing the second chip to be electrically connected to the substrate by bonding a plurality of first solder bumps to the active surface of the second chip and the lower surface of the substrate; a plurality of second solder bumps implanted on the lower surface of the substrate at an area exclusive of the second chip; a heat-dissipating device composed of a heat sink and a plurality of thermally conductive bumps, wherein the heat sink has an upper surface and a lower surface opposed to the upper surface, allowing the upper surface to be attached to the non-active surface of the second chip, and the thermally conductive bumps are implanted on the lower surface of the heat sink, and a circuit board for accommodating the thermally conductive bumps and the second solder bumps thereon in a manner that, the thermally conductive bumps are interposed between the heat sink and the circuit board, and the second solder bumps are interposed between the substrate and the circuit board.
The method for fabricating the above FCBGA semiconductor package comprises the steps of: preparing a substrate having an upper surface and a lower surface opposed to the upper surface; mounting at least one first chip on the upper surface of the substrate, allowing the first chip to be electrically connected to the substrate; mounting at least one second chip on the lower surface of the substrate in a flip chip manner, the second chip having an active surface and a non-active surface opposed to the active surface, allowing the second chip to be electrically connected to the substrate by bonding a plurality of first solder bumps to the active surface of the second chip and the lower surface of the substrate; implanting a plurality of second solder bumps on the lower surface of the substrate at an area exclusive of the second chip; preparing a heat-dissipating device composed of a heat sink and a plurality of thermally conductive bumps, wherein the heat sink has an upper surface and a lower surface opposed to the upper surface, allowing the upper surface to be attached to the non-active surface of the second chip, and the thermally conductive bumps are implanted on the lower surface of the heat sink; and providing a circuit board for accommodating the thermally conductive bumps and the second solder bumps thereon in a manner that, the thermally conductive bumps are interposed between the heat sink and the circuit board, and the second solder bumps are i
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Nelms David
Siliconware Precision Industries Co. Ltd.
LandOfFree
Flip-chip ball grid array semiconductor package with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flip-chip ball grid array semiconductor package with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flip-chip ball grid array semiconductor package with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3302957