Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-12
2004-06-15
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S287000, C438S288000, C438S591000
Reexamination Certificate
active
06750102
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improvements in semiconductor non-volatile memory transistors, and more specifically improvements in the gate design and processing of non-volatile transistors used in electrically erasable, electrically programmable read-only memories.
2. Description of the Related Art
Until recently, the gate structure of non-volatile memory transistors has been designed in a similar manner to that of conventional CMOS insulted gate field effect transistors (IGFETs) or MOSFETs. The difference between CMOS IGFETs and non-volatile IGFETs is primarily that non-volatile IGFETs include an added charge storage layer embedded in the gate dielectric. The charge storage layer is either a conductive element, such as a polycrystalline silicon (poly) floating gate, or a non-conductive element such as a dielectric which is capable of trapping charge. Older types of CMOS transistors have typically used a heavily doped N-type gate material for both N- and P-channel transistors in order to simplify processing and to achieve low poly resistivity. With the advent of deep sub-micron CMOS technology, a greater emphasis has been placed on reduced temperature processing, deeply scaled transistor geometries, and silicided polycrystalline silicon gates. This emphasis has led to changes in the gate structure that affect the doping of the poly.
In older technologies, the poly was typically doped by furnace diffusion processes using POC1
3
or Phosphine gas to produce a heavily doped N-type material. In newer technologies with channel length geometries at 0.7 microns and below, the furnace diffusion doping processes have been replaced with ion-implantation or low temperature in-situ doping during the poly deposition. These newer doping methods, which allow for substantially reduced thermal processing while doping the poly gate, are necessary to produce deeply scaled transistor geometries. Further, these newer doping methods allow for better doping control in the poly which is useful in facilitating the formation of a metal-silicide layer on top of the poly. Also, in newer technologies, it has been advantageous to use both N- and P-type doped poly, rather than simply N-type poly. Using P-type poly allows deeply scaled P-type MOS transistors to operate more efficiently at lower channel lengths due to the elimination of a buried channel that is usually required with N-type poly. Thus, N-type poly gates are often used in today's N-channel MOSFETs and P-type poly gates are often used in today's advanced P-channel MOSFETs. In these modern devices, the gate doping type is matched to the source and drain junction doping type.
Until recently, there has been no advantage in using different criteria for choosing a gate doping type for non-volatile memory devices from those used to choose the doping type for conventional MOSFETS. The choice has been primarily motivated by a desire to save costs by being compatible with processes used to produce conventional MOSFET devices. As a result, more recently developed doping methods and doping types for conventional MOSFETs have been applied to the construction of non-volatile memory transistors. Specifically, advanced N-channel non-volatile memory transistors are constructed using an N-type poly gate, advanced P-channel transistors are constructed using a P-type poly gate, and doping levels in both are often lower than what was used in the past.
In
FIG. 1
memory transistor
10
shows an N-channel non-volatile insulated gate field effect transistor which includes a charge storage layer
32
embedded in its gate dielectric, according to prior art. The charge storage layer
32
is typically surrounded by at least a top dielectric
31
and a bottom dielectric
33
and resides between the N-type gate
12
and the channel
15
of the transistor. Channel
15
resides in the P-type silicon bulk
11
between the N-type source
14
and N-type drain
16
regions. The charge storage layer
32
is either a “floating gate”, typically of doped polycrystalline silicon, or a dielectric material capable of trapping charge carriers such as silicon nitride, silicon oxynitride, silicon-rich silicon dioxide, or a ferroelectric material. The thickness of the gate dielectric, the composite of layers
31
,
32
and
33
, is typically dielectrically equivalent to 150 Å to 200 Å of silicon dioxide, although thinner dielectrics are currently under investigation. Note that transistor
10
could optionally include a silicide layer on top of the N-type gate
12
.
In
FIG. 2
memory transistor
10
′ shows a P-channel non-volatile insulated gate field effect transistor which includes a charge storage layer
32
embedded in its gate dielectric, according to prior art. The charge storage layer
32
is typically surrounded by at least a top dielectric
31
and a bottom dielectric
33
and resides between the P-type gate
12
′ and the channel
15
′ of the transistor. Channel
15
′ resides in the N-type silicon bulk
11
′ between the P-type source
14
′ and P-type drain
16
′ regions. The charge storage layer
32
is either a “floating gate”, typically of doped polycrystalline silicon, or a dielectric material capable of trapping charge carriers such as silicon nitride, silicon oxynitride, silicon-rich silicon dioxide, or a ferroelectric material. The thickness of the gate dielectric, the composite of layers
31
,
32
and
33
, is typically dielectrically equivalent to 150 Å to 200 Å of silicon dioxide, although thinner dielectrics are currently under investigation. Note that transistor
10
′ could optionally include a silicide layer on top of the P-type gate
12
′.
The amount and polarity of charge residing in the charge storage layer
32
affect the conductivity of the non-volatile transistor. The words “programmed” and “erased” are used here to describe two possible conductivity states that non-volatile transistors can achieve under two different charge storage conditions. It is recognized that the designation of the words “programmed” and “erased” is purely arbitrary and that these terms can be selected to represent different meanings depending on the application. Here, however, the terms “erased” and “programmed” are used in reference to relative levels of conductance. The terms “erased” or “erase”, and “programmed” or “program” are used to describe the “on” and “off” states, respectively. The primary difference between these two states is the level of conductance in non-volatile transistor while under read biases. An “on” state results when the non-volatile transistor is conductive and an “off” state results when the non-volatile transistor is non-conductive, or at least less conductive than a predetermined range of conductance that represents the “on” state. Further, the term “write” is used to describe an operation that intentionally sets the threshold voltage of a non-volatile memory transistor, either to the erase state or to the program state.
Unfortunately, we have discovered that matching the doping type of the gate to that of the source and drain junctions is not necessarily the optimal choice for building modern non-volatile memory transistor. So effects of using opposite gate and junction doping in non-volatile memory transistors are now being explored. The problem is that the traditional choice can lead to slow program timing and can reduce the scalability of a non-volatile transistor. These problems have not been a factor in devices that have been in production to date. However, as non-volatile device channel length geometries scale to 0.7 micron and below where the effective gate dielectric thickness is 170 Å or less the effects of gate doping become critical to the operation of the non-volatile transistor, as discussed below.
Non-volatile memory transistors oftentimes are written by placing a relatively high voltage on the gate with respect to the transistor channel. For example, a large negative potential (−10 to −20
Bachand Richard
Brophy Jamie L.
Cypress Semiconductor Corporation
Sako Bradley T.
Zarabian Amir
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