Structure of integrated trace of chip package

Details Structure of integrated trace of chip package Structure of integrated trace of chip package

2003-04-14

2004-12-28

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S781000, C257S784000

Reexamination Certificate

active

06836023

ABSTRACT:

BACKGROUND OF THE INVENTION
A semiconductor die with an integrated circuit has conductive pads formed at the periphery of the top surface of the die. Wires can be used to connect conductive pads in the semiconductor die to pads on a package substrate.
As the complexity of electronic circuitry increases, the conductive pads (that form inputs and outputs) in the semiconductor die are formed more closely together, thereby reducing the pad pitch. The lengths of wires are longer and the widths are narrower when the pad pitch is reduced. Increasing the lengths of the bonding wires increases the inductances in the wires, which reduces the speed of the circuitry.
Instead of wires, solder joints can be used to directly connect the pads in a semiconductor die to a circuit substrate, thereby providing shorter connection distances between the semiconductor die and the substrate. Solder joints form more stable joints than wire bonds. The switch from integrated circuit packages that are molded to chip scale packages or flip chip packages is a trend in the semiconductor industry.
However, the unmatched CTE (coefficient thermal expansion) between silicon in a semiconductor die and the mounting board (to which the die is mounted) requires larger and higher solder balls to fulfill solder joint reliability requirements. Unfortunately, this is contrary to another trend in the industry, which is to form thin, small and low profile packages for mobile electronic devices.
The bump pitch associated with an integrated circuit in a semiconductor die is much smaller than the pitch of conductive regions on a mounting board. Some have used redistribution traces comprising an underbump metallurgy to relocate the bond pads on integrated circuits to match the spacings of the conductive regions (e.g., conductive pads) on a mounting board.
Some have described the use of two dielectric layers including polyimide and BCB (benzcyclobutane) to fulfill the above design requirement. However, having two dielectric layers on a semiconductor die can cause many process and stress problems. First, the aluminum bond-pad in the die, the UBM of the redistributing trace, and two dielectric layers form a complicated structure that is difficult to manufacture. Second, the unmatched CTE of each material induces thermal stress in the integrated circuits below the dielectric layers, thereby damaging the integrated circuits when the dielectric layers are cured at high temperatures. Two layers of dielectric material will cause more thermal stress than one layer. Third, when coating and curing the second dielectric over the first cured dielectric layer, the interface bonding strength is lower than bonding two uncured dielectric layers. Fourth, there is also a cleaning process before coating the second dielectric layer. The interface strength will be influenced if the cleaning process is not complete.
In addition, the above-described processes are used for a semiconductor die that has inputs and outputs at the front side of the die. A protective back coating comprising an epoxy coating or other dielectric material is on the backside of the die. Because the backside of the semiconductor die is coated with a dielectric coating, the described processes are not suitable for die packages that include vertical MOSFET devices. In a vertical MOSFET, current passes from an input (e.g., a source region) at one side of the die to an output (e.g., a drain region) at the other side the die.
Embodiments of the invention address these and other problems.
SUMMARY OF THE INVENTION
Embodiments of the invention are directed to chip scale semiconductor die packages and methods for making chip scale semiconductor die packages.
One embodiment of the invention is directed to a semiconductor die package comprising: (a) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side; (b) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture; (c) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad; (d) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer; and (e) a solder structure on the underbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layer.
Another embodiment of the invention is directed to a method of processing a semiconductor die, the method comprising: (a) providing a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side; (b) forming a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture; (c) forming an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad; (d) forming a single dielectric layer over the underbump metallurgy layer, wherein the single dielectric layer comprises a second aperture on and in direct contact with the underbump metallurgy layer; and (e) forming a solder structure on the underbump metallurgy layer and within the second aperture of the dielectric layer.
Another embodiment of the invention is directed to an electrical assembly comprising: (a) a circuit substrate including a plurality of conductive regions; and (b) a semiconductor die package comprising (i) a semiconductor die comprising a first side and a second side, a vertical transistor, and a bond pad at the first side, (ii) a passivation layer having a first aperture on the first side, where the bond pad is exposed through the first aperture, (iii) an underbump metallurgy layer on and in direct contact with the passivation layer, wherein the underbump metallurgy layer is at least partially within the first aperture and contacts the bond pad, (iv) a single dielectric layer comprising a second aperture on and in direct contact with the underbump metallurgy layer, and (v) a solder structure on the underbump metallurgy layer, the solder structure being within the second aperture of the single dielectric layer, wherein the solder structure is coupled to a conductive region within the plurality of conductive regions.
These and other embodiments are described below.


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