Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-11-09
2004-06-29
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000
Reexamination Certificate
active
06756262
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to a semiconductor device and to the production thereof. More particularly, this invention relates to technology that is effective when applied to a semiconductor device having a DRAM (Dynamic Random Access Memory).
Memory cells of a DRAM are generally arranged at points of intersection between a plurality of word lines and a plurality of bit lines that are arranged in the form of a matrix on a main plane of a semiconductor substrate. Each memory cell comprises one MISFET (Metal Insulator Semiconductor Field Effect Transistor) for selecting the memory cell and one information storage capacitance device (capacitor) connected in series with this MISFET.
The MISFET for selecting the memory cell is formed in an active region encompassed by a device isolation region, and comprises mainly a gate oxide film, a gate electrode formed integrally with a word line and a pair of semiconductor regions constituting a source and a drain. Generally, two of such MISFETs are formed in one active region, and one of the source/drain (semiconductor regions) of these two MISFETs is shared at the center of the active region. The bit line is disposed over the MISFET and is connected electrically to the semiconductor region thus shared. The capacitor is disposed likewise over the MISFET and is connected electrically to the other source/drain.
Japanese Patent Laid-open No. 7084/1995, for example, discloses a DRAM having a Capacitor-Over-Bit-line (COB) structure formed by disposing the capacitors over the bit lines. The DRAM described in this reference employs a structure in which a lower electrode (accumulation electrode) of each capacitor arranged over the bit line is processed into a cylindrical shape, and a capacitance insulating film and an upper electrode (plate electrode) are formed on this lower electrode. Being shaped into a cylindrical shape, the surface of the lower electrode can be increased so as to supplement the decrease of the storage charge quantity (Cs) of the capacitor resulting from miniaturization of the memory cell. In the memory cell having such a COB structure, cubing of the capacitor structure to a certain extent is essentially necessary in order to secure the desired operation reliability as a semiconductor memory device.
It is anticipated, however, that even the cubing of the capacitor structure will not be sufficient to secure the necessary capacitance value (storage charge quantity) in the latest semiconductor devices that are highly integrated, particularly in those which have a capacity of 256 Mbit (megabit) or more.
The journal “Applied Physics”, Vol. 65, No. 11, pp. 1111-1112, published by the Society of Applied Physics, Nov. 10, 1996, examines the possibility of the use of high dielectric materials (ferroelectric materials), such as tantalum oxide (Ta
2
O
5
) or STO (SrTO
3
) or BST (Ba
x
Sr
1−x
TO
3
), for the insulating film of the capacitor. Ta
2
O
5
has a specific inductive capacity of as high as about 20, and STO and BST have an extremely high specific inductive capacity of about 200 to about 500. Therefore, if these high dielectric constant films are used, a higher capacitance value could be acquired more easily than the silicon oxide film and the silicon nitride film that have been used in the past. STO and BST, in particular, have a high dielectric constant, and are therefore expected to exhibit a remarkable effect of increasing the capacitance value.
Film formation of STO and BST is conducted in an oxidizing atmosphere. Therefore, when the silicon materials that have been used in the past are used for the capacitor electrode, a silicon oxide film having a low dielectric constant is formed undesirably on the electrode interface. For this reason, the possible use of Ru (ruthenium), Pt (platinum), RuO
2
(ruthenium oxide), etc, having a high oxidation resistance has been examined as the electrode material for the capacitor.
SUMMARY OF THE INVENTION
However, the inventors of this invention have confirmed that the following problems arise when precious metals, such as Ru, Pt, etc, or their suicides or oxides, are used for the electrode materials, particularly for the upper electrode. The problems that will be explained below are not particularly known in the art, but have been discovered as a result of experiments conducted by the present inventors. Incidentally, the term “precious metal” as used in this specification refers to gold (Au), silver (Ag) and platinum group metals (ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) and platinum (Pt)).
The first problem is that when a precious metal is used for the upper electrode, the electric connection between a contact portion (through-hole plug) with the upper layer wire and the upper electrode becomes unstable, or a connection defect arises.
The first cause of this problem is oxygen contained in the precious metal that forms the upper electrode. A CVD process is employed when the film of the precious metal such as Ru or Pt is formed. Since the starting gas contains oxygen in this CVD process, the resulting precious metal film contains oxygen, too. Also, the re is the case where the film constituent elements contain oxygen from the beginning such as in the case of RuO
2
. To open a through-hole for the connection to the upper electrode in an inter-layer insulating film covering the upper electrode, a photoresist film is used generally. However, when this photoresist film is removed by ashing, the upper electrode (film made of the precious metal) below the through-hole absorbs oxygen in the ashing atmosphere. When heat-treatment is conducted after the through-hole plug is formed, oxygen in the film reacts with the metal constituting the plug and forms a metal oxide. The plug comprises generally a barrier metal such as titanium nitride and a main conductor layer such as tungsten. In this case, titanium in the barrier metal reacts with oxygen and forms titanium oxide having a high resistivity. Since such titanium oxide is formed structurally between the upper electrode and the plug, the electric contact between the upper electrode and the plug is impeded, so that the problem of unstableness (drop of connection reliability) of the electric connection described above occurs.
The second cause is that an etching selection ratio cannot be balanced substantially between the precious metal constituting the upper electrode and a silicon oxide film serving as the inter-layer insulating film that covers the upper electrode. The through-hole for the connection to the upper electrode is formed when the opening is bored in the silicon oxide film serving as the inter-layer-insulating film. Dry etching of the silicon oxide film is generally conducted using a photoresist film as a mask to bore this opening. In this instance, since the etching selection ratio cannot be balanced sufficiently between the silicon oxide film and the precious metal constituting the lower electrode, the through-hole is formed in such a fashion as to penetrate through the upper electrode. Since the through-hole is so formed as to penetrate through the upper electrode in this way, the contact and the area between the plu upper electrode inside the through-hole becomes small and the problem of the drop of connection reliability develops. It may be possible to control the etching time so that etching can be completed on the surface of the upper electrode, but this method is difficult in actual practice for the following reasons. The supply of power to the upper electrode is provided from its upper layer wire through the through-hole plug. However, the supply of power or the connection of the wire from the upper layer wire is made also to the wire (first layer wire) that is formed in the same wire layer as the bit lines. In other words, two or more kinds of through-holes, that is, the through-hole for the plug for the connection to the upper electrode and the through-hole for the plug for the connection to the first layer wire, exist. Since the bit line (first layer wire) is f
Asano Isamu
Hirasawa Masayoshi
Nakamura Yoshitaka
Ohji Yuzuru
Sekiguchi Tomonori
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Lee Eddie
Owens Douglas W.
LandOfFree
Semiconductor integrated circuit device having spaced-apart... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device having spaced-apart..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device having spaced-apart... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3294248