Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-01
2004-06-29
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000, C438S654000, C438S685000, C438S785000
Reexamination Certificate
active
06756298
ABSTRACT:
TECHNICAL FIELD
The present invention concerns methods of semiconductor device or integrated circuit manufacturing, particularly methods of forming interconnects from copper and other metals.
BACKGROUND OF THE INVENTION
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together with aluminum wires to define a specific electric circuit, such as a computer memory.
To form the aluminum wires, fabricators sometimes use a dual-damascene metallization technique, which takes its name from the ancient Damascan metalworking art of inlaying metal in grooves or channels to form ornamental patterns. The dual-damascene technique entails covering the components on a wafer with an insulative layer of silicon dioxide, etching small holes in the insulative layer to expose portions of the components underneath, and subsequently etching shallow trenches from hole to hole to define a wiring pattern. Fabricators then blanket the entire insulative layer with a thin sheet of aluminum and polish off the excess, leaving behind aluminum vias, or contact plugs, in the holes and thin aluminum wires in the trenches. The aluminum wires are typically about one micron thick, or about 100 times thinner than a human hair.
In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. See, for example, D. Edelstein et al., Full Copper Wiring in a Sub-0.25 um CMOS ULSI Technology, Technical Digest of 1997 IEDM, p. 773-776, 1997; and S. Venkatesan et al., A High Performance 1.8V, 0.20 um CMOS Technology with Copper Metallization, Technical Digest of 1997 IEDM, p. 769-772, 1997. Moreover, Applied Materials, Inc., a maker of semiconductor fabrication equipment, reports special equipment for fabricating copper-wired integrated circuits. (Applied Materials Announces First Barrier/Seed Layer System for Copper Interconnects, http:// www.appliedmaterials.com
ewsroonm/pr-00103.html, Dec. 2, 1997.)
These copper-wired integrated circuits typically follow a variation of the dual-damascene method, which entails forming a copper-diffusion barrier in holes and trenches prior to filling them with copper. The typical copper-diffusion barrier is more than 30-nanometers thick and consists of tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium nitride (TiN), or tungsten nitride (WN). Filling the barrier-lined holes and trenches with copper generally entails forming a thin copper seed layer on the copper-diffusion barrier and then electroplating copper on the seed layer to finish.
The present inventors identified at least two problems with current techniques for making the copper wiring. The first is that typical copper-diffusion barriers add appreciable resistance to the copper wiring, and thus negate some of the advantages of using copper. The second concerns the use of separate wafer-processing chambers to form the copper-diffusion barrier and the copper seed layer. Using two chambers means that wafers are processed in one chamber to form the diffusion barrier and then transported to another chamber to form the seed layer. However, moving wafers from one chamber to another not only slows down fabrication, but also risks the addition of undesirable particles to the wafers, some of which can cause defects in resulting integrated circuits.
Accordingly, there is a need for better ways of making copper wiring in integrated circuits.
SUMMARY OF THE INVENTION
To address these and other needs, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition, two processes which facilitate formation of copper-diffusion barriers and seed layers within the chamber. One of the unique methods of forming barrier and seed layers entails forming a graded composition of tungsten silicide (WSi
x
), nitriding the graded composition, and then depositing a copper seed layer on the nitrided composition, all within a single wafer-processing chamber to promote fabrication efficiency and reduce defects.
REFERENCES:
patent: 2842438 (1958-07-01), Saarivirta et al.
patent: 3954570 (1976-05-01), Shirk et al.
patent: 4386116 (1983-05-01), Nair et al.
patent: 4394223 (1983-07-01), Hall
patent: 4423547 (1984-01-01), Farrar et al.
patent: 4565157 (1986-01-01), Brors et al.
patent: 4574095 (1986-03-01), Baum et al.
patent: 4762728 (1988-08-01), Keyser et al.
patent: 4788082 (1988-11-01), Schmitt
patent: 4847111 (1989-07-01), Chow et al.
patent: 4931410 (1990-06-01), Tokunaga et al.
patent: 4948459 (1990-08-01), van Laarhoven et al.
patent: 4962058 (1990-10-01), Cronin et al.
patent: 4996584 (1991-02-01), Young et al.
patent: 5019531 (1991-05-01), Awaya et al.
patent: 5034799 (1991-07-01), Tomita et al.
patent: 5084412 (1992-01-01), Nakasaki
patent: 5100499 (1992-03-01), Douglas
patent: 5130274 (1992-07-01), Harper et al.
patent: 5149615 (1992-09-01), Chakravorty et al.
patent: 5158986 (1992-10-01), Cha et al.
patent: 5173442 (1992-12-01), Carey
patent: 5231056 (1993-07-01), Sandhu
patent: 5240878 (1993-08-01), Fitzsimmons et al.
patent: 5243222 (1993-09-01), Harper et al.
patent: 5256205 (1993-10-01), Schmitt, III et al.
patent: 5334356 (1994-08-01), Baldwin et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5371042 (1994-12-01), Ong
patent: 5384284 (1995-01-01), Doan et al.
patent: 5413687 (1995-05-01), Barton et al.
patent: 5426330 (1995-06-01), Joshi et al.
patent: 5442237 (1995-08-01), Hughes et al.
patent: 5447887 (1995-09-01), Filipiak et al.
patent: 5470789 (1995-11-01), Misawa
patent: 5470801 (1995-11-01), Kapoor et al.
patent: 5476817 (1995-12-01), Numata
patent: 5495667 (1996-03-01), Farnworth et al.
patent: 5506449 (1996-04-01), Nakano et al.
patent: 5529956 (1996-06-01), Morishita
patent: 5538922 (1996-07-01), Cooper et al.
patent: 5539060 (1996-07-01), Tsunogae et al.
patent: 5595937 (1997-01-01), Mikagi
patent: 5609721 (1997-03-01), Tsukune et al.
patent: 5625232 (1997-04-01), Numata et al.
patent: 5635253 (1997-06-01), Canaperi et al.
patent: 5654245 (1997-08-01), Allen
patent: 5662788 (1997-09-01), Sandhu et al.
patent: 5670420 (1997-09-01), Choi
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5675187 (1997-10-01), Numata et al.
patent: 5679608 (1997-10-01), Cheung et al.
patent: 5681441 (1997-10-01), Svendsen et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5719089 (1998-02-01), Cherng et al.
patent: 5719410 (1998-02-01), Suehiro et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5763953 (1998-06-01), Iljima et al.
patent: 5780358 (1998-07-01), Zhou et al.
patent: 5785570 (1998-07-01), Bruni
patent: 5792522 (1998-08-01), Jin et al.
patent: 5801098 (1998-09-01), Fiordalice et al.
patent: 5821168 (1998-10-01), Jain
patent: 5824599 (1998-10-01), Schacham-Diamond et al.
patent: 5891797 (1999-04-01), Farrar
patent: 5891804 (1999-04-01), Havemann et al.
patent: 5893752 (1999-04-01), Zhang et al.
patent: 5895740 (1999-04-01), Chien et al.
patent: 5897370 (1999-04-01), Joshi et al.
patent: 5907772 (1999-05-01), Iwasaki
patent: 5911113 (1999-06-01), Yao et al.
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5925930 (1999-07-01), Farnworth et al.
patent: 5930669 (1999-07-01), Uzoh
patent: 5932928 (1999-08-01), Clampitt
patent: 5933758 (1999-08-01), Jain
patent: 5948467 (1999-09-01), Nguyen et al.
patent: 5962923 (1999-10-01), Xu et al.
patent: 5968333 (1999-10-01), Nogami et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5972179 (1999-10-01), Chittip
Ahn Kie Y.
Forbes Leonard
Lebentritt Michael S.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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