Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-13
2004-06-22
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S255000, C438S398000, C438S592000
Reexamination Certificate
active
06753226
ABSTRACT:
TECHNICAL FIELD
The present invention relates to methods for manufacturing semiconductor devices that mix-mount DRAMs (Dynamic Random Access Memories) and other device elements in the same chip, and semiconductor devices manufactured thereby.
BACKGROUND
In recent years, the mixed-mounting of various types of circuits is required in consideration of various factors, such as, for example, to shorten the chip interface delay, to reduce the cost per board area, and to reduce the cost in design and development of boards. There are problems in the mix-mounting technology in that the process becomes complex and the IC cost increases.
SUMMARY
One embodiment of the present invention relates to a method for manufacturing a semiconductor device, the semiconductor device having a DRAM located in a memory cell region and a field effect transistor located in a field effect transistor region that is a region other than the memory cell region. The method includes (a) forming a capacitor for the DRAM; and (b) after step (a), forming a silicide layer at a source/drain region of the field effect transistor.
Another embodiment relates to a method for manufacturing a semiconductor device, the semiconductor device having a DRAM located in a memory cell region, a first field effect transistor that is located in a peripheral circuit region and becomes a component of a peripheral circuit for the DRAM, and a second field effect transistor located in a region other than the memory cell region and the peripheral circuit region. The method includes (A) forming the first field effect transistor with a source/drain that does not have a silicide layer in the peripheral circuit region. Step (B), after step (A), includes forming a capacitor for the DRAM. Step (C), after step B, includes forming a silicide layer at a source/drain of the second field effect transistor.
Another embodiment relates to a semiconductor device including a DRAM located in a memory cell region, and a field effect transistor located in a field effect transistor region that is a region other than the memory cell region. The device also includes silicide layers formed at a cell plate that is a component of a capacitor of the DRAM and at a source/drain that is a component of the field effect transistor. In addition, silicide layers are not formed at a source/drain that is a component of a memory cell selection field effect transistor of the DRAM.
Another embodiment relates to a semiconductor device including a DRAM located in a memory cell region. The device also includes a first field effect transistor that is located in a peripheral circuit region and becomes a component of a peripheral circuit for the DRAM, and a second field effect transistor located in a region other than the memory cell region and the peripheral circuit region. The device also includes silicide layers formed at a cell plate that is a component of a capacitor of the DRAM and at a source/drain of the second field effect transistor. In addition, silicide layers are not formed at a source/drain that is a component of a memory cell selection field effect transistor of the DRAM or at a source/drain of the first field effect transistor.
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Sato Hisakatsu
Tsugane Hiroaki
Konrad Raynes & Victor LLP
Lebentritt Michael S.
Raynes Alan S.
Seiko Epson Corporation
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