Method of forming integrated circuit contacts

Details Method of forming integrated circuit contacts Method of forming integrated circuit contacts

2003-01-24

2004-12-21

Gurley, Lynne A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S256000, C438S381000, C438S396000, C438S399000, C438S623000, C438S624000, C438S634000, C438S637000, C438S666000

Reexamination Certificate

active

06833300

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuit manufacturing and more particularly to a method for forming contacts to electronic devices.
BACKGROUND OF THE INVENTION
Integrated circuits comprise electronic devices such as transistors, resistors, and capacitors formed on a semiconductor substrate. The individual electronic devices are interconnected using a number of layers of metal interconnects formed in alternating dielectric layers above the surface of the semiconductor substrate containing the devices. Each electronic device that comprises the integrated circuit has to be connected to the metal lines through the dielectric layers that overlie the semiconductor substrate surface. Typically a pre-metal dielectric (PMD) layer is formed over the semiconductor substrate following the formation of the electronic devices in the semiconductor substrate. Electrical contact is made to the underlying electronic devices by forming openings in the PMD layer and filling the openings with a conductive plug formed using a conductive material such as titanium nitride, tungsten, or aluminum. The conductive plug (or plug) formed in the openings will allow an electrical connection to be made from the electronic devices to the various metal layers formed above the PMD layer. An example of such an electrical connection made to a typical metal oxide semiconductor (MOS) transistor is shown in FIG.
1
.
Shown in
FIG. 1
is a typical MOS transistor fabricated using standard integrated circuit processing methodology. Isolation regions
20
are formed in a semiconductor
10
. A transistor gate stack comprising a gate dielectric layer
30
and a gate electrode
40
is formed on the surface of the semiconductor
10
. The gate electrode usually comprises a conductive material such as doped polycrystalline silicon and various metals and silicides. Typical thicknesses for the transistor gate stack are between 800A and 5000A. Following the formation of the transistor gate stack a number of self-aligned implants are performed. These self-aligned implants include drain/source extension implant and pocket implants. The self-aligned implants that are aligned to the transistor gate stack will result in the formation of the doped regions
50
in the semiconductor
10
. Sidewall structures
60
are formed adjacent to the gate electrode
40
using standard processing technology. The sidewall structures
60
typically comprise dielectric material such as silicon oxide, silicon nitride, or any other suitable dielectric material. Following the formation of the sidewall structures
60
, the transistor source and drain regions
70
are formed by implanting suitable dopants into the semiconductor
10
. Following the formation of the source and drain regions
70
, metal silicide layers
80
and
90
and formed on the source and drain regions
70
and the gate electrode
40
respectively. The metal silicide layers
80
and
90
will reduce the contact resistance between the MOS transistor and the metal layers. A PMD layer
100
is formed over the MOS transistor as shown in Figure and openings are
110
and
120
are formed in the PMD layer. Conductive plugs will be formed in the openings and the openings are formed using standard integrated circuit processing techniques.
Typically the openings
110
and
120
are formed by first forming patterned photoresist on the PMD layer. The patterned photoresist will then act as a mask during the subsequent contact etching process used to form the openings. It should be noted that the silicide layer
90
formed on the gate electrode
40
is about 800A to 5000A above the silicide layer
80
formed on the source drain regions. This topographic variation makes performing the contact etch down to the various silicide layers difficult. The different height of the various silicide layers
80
and
90
imply that the etch times required to form the various openings are different. A major problem with forming the openings is that completing the contact etch to the deeper silicide layers
80
may cause the shallower contact etch (i.e. the etch to silicide layer
90
) to continue through silicide layer
90
removing a significant portion of the silicide layer
90
. This problem is often addressed by reducing the etch times for forming the deeper openings
110
. However reducing the etch time for the deeper openings may lead to under-etched openings resulting in an increased contact resistance.
Topology variations across the wafer also require that the contact etch process contain about a 50% over-etch to ensure that all the openings across the semiconductor wafer are properly formed. This large over-etch results in large contact resistance variations across the semiconductor wafer that make it more difficult to form precision integrated circuits. In addition to the above described MOS transistor other devices such as bipolar junction transistors (BJT) and metal-insulator-metal (MIM) capacitors are also susceptible to the above described contact etch problems. There is therefore a need for a method of forming integrated circuits that reduces and/or eliminates the contact etch formation problems. The instant invention addresses this need.
SUMMARY OF THE INVENTION
The instant invention is a method for forming electrical contacts to electronic devices formed as part of an integrated circuit. A conductive layer is formed on electronic device such as a MOS transistor, capacitor, or bipolar junction transistor. An optional first dielectric layer is formed over the conductive layer and a carbon containing dielectric layer formed over the optional dielectric layer if present. A PMD dielectric layer is formed over the carbon containing dielectric layer and openings are formed in the PMD layer. The openings are formed over the conductive layer, the optional dielectric layer, and the carbon containing dielectric layer. The exposed regions of the carbon containing dielectric layer and the optional dielectric layer (if present) are removed to expose the underlying conductive layer. A conductive material is then used to fill the opening and electrically contact the conductive layer formed on the electronic device.


REFERENCES:
patent: 6261892 (2001-07-01), Swanson
patent: 6596581 (2003-07-01), Park et al.
patent: 2003/0027385 (2003-02-01), Park et al.

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