Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-21
2004-11-30
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S386000, C438S788000, C438S792000
Reexamination Certificate
active
06825079
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for producing a horizontal insulation layer on a conductive material within a trench formed in a semiconductor substrate. The horizontal insulation layer also involves, in particular, so-called oxide covers for electrically insulating the conductive trench filling from components applied on the semiconductor substrate.
Trenches are formed in a semiconductor substrate for example in order to provide trench capacitors having the highest possible capacitance for memory cells in an integrated circuit. A typical memory cell contains a selection transistor with a gate terminal, a source terminal and a drain terminal. The gate is connected to a word line, so that it is possible to control the conductivity of the channel region of the transistor, the channel region lies below the gate in the substrate. By way of example, the source terminal in the substrate on one side of the channel region is connected to a bit line contact for the read-out of a memory information item. The drain terminal on the other side of the channel region in the substrate, which has the same conductivity type as the source terminal but an opposite conductivity type to the channel region, is connected to one of the two capacitor electrodes via a contact.
The trench capacitor essentially contains the conductive trench filling as a first trench electrode, a thin dielectric layer in a lower region of the trench and a counter electrode on the substrate side, the counter electrode usually formed as a doped buried well and is connected to a given potential across a plurality of adjacent trenches. An information item is stored in the memory cell by an electrical charge being read into the conductive filling of the first capacitor electrode in the trench capacitor.
For cost and performance reasons, the aim is often to achieve the highest possible densities of memory cells in an integrated circuit. Therefore it is endeavored to keep the space required by the selection transistor on the semiconductor substrate besides the trench capacitor area as small as possible. Two solutions have been proposed for this purpose: the selection transistor is formed at least partly above the trench in a planar manner—source and drain terminals are at the same level at the surface of the substrate—or within the trench in a vertical configuration—source and drain terminals are disposed one above the other, e.g. in the substrate at the inner wall of the trench. In both cases, the problem arises here that the electrically conductive trench filling which takes up the charge to be stored is not permitted to be directly connected to the overlying gate electrode. Therefore, it is necessary to form an insulation layer to insulate the conductive trench filling from electrically conductive structures disposed on the surface. This also applies, in particular, to the conventional case where, by way of example, a word line that passes the trench above its superficial opening and serves for connecting only adjacent cells has to be insulated from the conductive trench filling of a trench capacitor.
The formation of insulation layers for the above-mentioned embodiments configured as vertical transistors is described for example in U.S. Pat. Nos. 6,177,698 B1, 6,184,091 B1, and 6,074,909. In the document mentioned last, by way of example, an insulation layer is applied in a conformal deposition method on the conductive filling and the sidewalls of the trench, after which a sacrificial layer having a large layer thickness is deposited onto the substrate and into the trench in a manner such that it fills the latter. The layer is subsequently etched back, so that it only covers the planar bottom region and the lower part of the sidewalls covered with the conformal insulating layer in the trench. Afterward, in an isotropic etching step that is carried out selectively with respect to the material of the sacrificial layer, that region of the conformal insulating layer that is not covered by the sacrificial layer is removed, followed by a removal of the sacrificial layer as well. Consequently, the horizontal insulating layer covering the conductive filling of the trench and having the original deposition thickness remains in the bottom region of the trench.
The source and drain regions, the gate oxide and the gate are subsequently formed in the trench by the deposition of a further conductive filling. The method described for forming an insulating layer as an oxide cover in the trench can also be used when fabricating memory cells with planar selection transistors. As is described in Published, Non-Prosecuted German Patent Application DE 199 41 147 A1, corresponding to U.S. Pat. No. 6,326,262, for example, in order to form a space-saving memory cell in which the planar selection transistor is disposed above the trench, a monocrystalline epitaxial layer is grown above the oxide cover—already formed—from the sidewalls of the trench, which epitaxial layer terminates the oxide cover from above. The connection of the underlying conductive filling of the trench capacitor is opened in the further course of the process after the completion of the word lines in a self-aligned manner with respect to the selection transistors, in order to ensure a connection of the trench capacitor to the selection transistor. In the case of such a configuration, also called a device-on-trench cell (DOT cell), particular requirements are made of the properties of the insulating layer as the oxide cover. Specifically, a very small layer thickness must be present, in particular, in order to enable an opening of the insulating layer for the purpose of forming the contact to the conductive filling. In this case, a thickness of 20-30 nm is sought, for example.
In order to avoid a contact with the channel or drain terminals of the selection transistor located laterally above the trench, there must also be a particularly small layer thickness variation for the insulating layer, so that a complete dielectric isolation with respect to the substrate is provided. To that end, the process for the overgrowth of the oxide cover during the selective epitaxy is to be carried out particularly carefully in order to avoid even only very slight defect densities. At the same time, however, the process must be compatible with the overall process in which feature sizes of less than 200 nm are fabricated.
Three approaches have been pursued hitherto for solving the problem:
a.) By way of example, the polysilicon of the trench capacitor filling has been thermally oxidized in order to form the insulation layer. In this case, the problem arises that oxide bridges form between adjacent trench capacitors and lead to an unsatisfactory growth of the epitaxial silicon layer, the so-called bird's beak.
b.) The above-described deposition of a thin oxide layer with subsequent back planarization, the so-called TEOS caps, which, however, lead to a very small process window, accompanied by the high risk of the edge regions of the oxide cover being opened.
c.) The deposition of an oxide layer from a high-density plasma (HDP) with subsequent planarization in a CMP step has additionally been proposed, which, however, disadvantageously leads to large layer thickness variations both within the integrated circuits and with systematic defects across the wafer surface. This makes it considerably more difficult to open the oxide covers for instance in a plasma-chemical process for the contact connection.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for producing a horizontal insulation layer on a conductive material in a trench that overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which an insulation layer is formed in a trench in the case of which a layer thickness to be attained is intended to be achieved with high accuracy in conjunction with particularly small layer thickness variation.
With the foregoing and other objects in view there is provided, in acc
Ghyka Alexander
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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