Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-06-21
2004-03-09
Cao, Phat X. (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000
Reexamination Certificate
active
06703272
ABSTRACT:
TECHNICAL FIELD
The invention pertains to methods of forming spaced conductive regions, and in particular aspects pertains to methods of forming capacitor constructions.
BACKGROUND OF THE INVENTION
Capacitor constructions are utilized in numerous semiconductor devices including, for example, dynamic random access memory (DRAM) devices. Capacitor constructions comprise a pair of conductive nodes separated from one another by dielectric material, and accordingly capacitively coupled with one another. The conductive components of capacitor constructions can comprise numerous materials, including, for example, metals, metal alloys, and conductively-doped semiconductive materials (such as, for example, conductively-doped silicon). There can be advantages to utilizing metals in capacitor constructions, and recently there have been efforts to incorporate various so-called noble metals into capacitor constructions. Exemplary noble metals are platinum, rhodium, iridium and ruthenium.
Various problems are encountered during attempts to incorporate noble metals into capacitor constructions. For instance, it is typically desired that an array of capacitor constructions be simultaneously formed. Ultimately, it is desired to form numerous conductive storage nodes associated with the array. The individual storage nodes are spaced from one another, and can accordingly be considered spaced conductive regions. However, it can be difficult to pattern various metals into spaced conductive regions. For instance, it is found that platinum will smear during various traditional semiconductor fabrication steps (such as, for example, chemical-mechanical polishing). The smearing can inhibit formation of a bottom electrode in a container.
In light of the above-described difficulties, it is desirable to develop new methods of forming spaced conductive regions associated with semiconductor constructions; and it is further desirable that such new methods be suitable for utilization in capacitor fabrication.
It is noted that although the invention was motivated by the problems discussed above, the invention is not to be limited to the applications discussed above except to the extent that the applications are expressly recited in the claims that follow.
SUMMARY OF THE INVENTION
In one aspect, the invention includes a method of forming spaced conductive regions associated with a semiconductor construction. For instance, an exemplary application of the invention is formation of a bottom electrode of a container capacitor. A construction is formed which includes a first electrically conductive material over a semiconductor substrate. Openings extend through the first electrically conductive material and into the semiconductor substrate. A second electrically conductive material is formed within the openings and over the first electrically conductive material. The second electrically conductive material comprises a different composition than the first electrically conductive material, and is in electrical contact with the first electrically conductive material. The second electrically conductive material is subjected to anodic dissolution. During the dissolution, the first electrically conductive material is electrically connected to a power source. The second electrically conductive material within the openings becomes electrically isolated from the first electrically conductive material as the dissolution progresses, and some of the second electrically conductive material remains within the openings in the substrate as spaced conductive regions after the anodic dissolution. The second electrically conductive material can be subsequently incorporated into a container-shaped capacitor as a bottom electrode.
In further aspects, the invention pertains to methods of forming capacitor constructions.
REFERENCES:
patent: 6037212 (2000-03-01), Chao
patent: 6171902 (2001-01-01), Ida
patent: 6458654 (2002-10-01), Clampitt
Sinha Nishant
Taylor Theodore M.
Cao Phat X.
Doan Theresa T.
Micro)n Technology, Inc.
Wells St. John P.S.
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