Semiconductor device including a field effect transistor and...

Details Semiconductor device including a field effect transistor and... Semiconductor device including a field effect transistor and...

2003-03-31

2004-11-23

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S241000, C438S981000, C438S250000, C438S253000, C438S396000

Reexamination Certificate

active

06821840

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of fabricating integrated circuits, and, more particularly, to the formation of semiconductor devices including field effect transistors, such as MOS transistors, and passive capacitors having a reduced leakage current.
2. Description of the Related Art
In modem integrated circuits, a huge number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors, and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with an improved degree of performance in terms of speed and power consumption. A reduction in size of transistor is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs, as the reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance and also power consumption, since, due to the reduced switching time period, the transient currents upon switching a CMOS transistor element from logic low to logic high are significantly reduced. On the other hand, the reduction of feature sizes, such as the channel length of the transistor elements in the deep sub-micron regime, entails a plurality of issues that may partially offset the advantages obtained by the improved switching performance. For example, reducing the channel length of field effect transistors requires the reduction of the thickness of the gate insulation layer in order to maintain a sufficiently high capacitive coupling of the gate electrode to the channel region so as to appropriately control the formation of the conductive channel upon application of a control voltage to the gate electrode. For highly sophisticated devices, currently featuring a channel length of 0.18 &mgr;m or even less, typically comprising silicon dioxide for the superior and well known characteristics of the interface between the silicon dioxide and the underlying channel region, a thickness of the gate insulation layer is on the order of 2-5 nm or even less. For a gate dielectric of this order of magnitude, it turns out that, in total, the leakage current passing through the thin gate dielectric may become comparable to the transient currents, since the leakage currents exponentially rise as the gate dielectric thickness is linearly reduced.
In addition to the large number of transistor elements, plural passive capacitors are typically formed in integrated circuits that are used for a plurality of purposes, such as for de-coupling purposes. Since these capacitors are usually formed in and on active semiconductor regions, acting as a first capacitor electrode, with a dielectric layer having characteristics in conformity with process requirements for the concurrently fabricated field effect transistors, and a second capacitor electrode formed of the gate electrode material, the problem of leakage current is significantly exacerbated owing to the large chip area occupied by these capacitor elements. Consequently, the capacitors significantly contribute to the total gate leakage consumption and, therefore, to the total power consumption of the integrated circuit. For applications requiring a minimum power consumption, such as portable battery-powered devices, the high amount of static power consumption may not be acceptable, and, therefore, usually a so-called dual gate oxide processing may be used to increase the thickness of the dielectric layer of the capacitors, thereby reducing the leakage current of these elements.
With reference to
FIGS. 1
a
-
1
c
, a typical prior art process flow for forming capacitors having a reduced leakage current will now be described.
FIG. 1
a
schematically shows a cross-sectional view of a semiconductor device
100
at an initial manufacturing stage. The semiconductor device
100
comprises a substrate
101
, for example a silicon substrate, including a first active semiconductor region
120
and a second active semiconductor region
130
, which are enclosed by respective isolation structures
102
. The second active region
130
and the corresponding isolation structure
102
are covered by a mask layer
103
that may be comprised of photoresist. The first active region
120
comprises a surface portion
104
having severe lattice damage caused by an ion implantation, as indicated by
105
.
A typical process flow for forming the semiconductor device as depicted in
FIG. 1
a
includes sophisticated photolithography and etch techniques for defining the isolation structures
102
followed by a further photolithography step to pattern the resist mask
103
. As these process techniques are well known in the art, a detailed description thereof is omitted. Subsequently, the ion implantation
105
is carried out with any appropriate ions, such as silicon, argon, xenon and the like, wherein a dose and energy is selected to create severe lattice damage in the portion
104
, thereby significantly changing the diffusion behavior of the portion
104
during an oxidation process that is to be carried out subsequently.
FIG. 1
b
schematically shows the semiconductor structure
100
in an advanced manufacturing stage. A first dielectric layer
121
, substantially comprised of silicon dioxide, and having a first thickness
122
, is formed on the first active region
120
. A second dielectric layer
131
having a second thickness
132
and comprised of the same material as the first dielectric layer
121
is formed on the second active region
130
. The first and the second dielectric layers
121
and
131
are formed by conventional oxidation in a high temperature furnace process or by a rapid thermal oxidation process. Due to the severe lattice damage of the surface portion
104
, the oxygen diffusion in this surface portion
104
is significantly enhanced compared to silicon portions having a substantially intact crystallinity, such as in the second active region
130
. Consequently, oxide growth in and on the first active region
120
is increased compared to the growth rate of the second active region
130
so that the second thickness
132
differs from the first thickness
122
by approximately 0.2-1.0 nm for a thickness of the second dielectric layer
131
on the order of 1-5 nm.
FIG. 1
c
schematically shows the semiconductor device
100
in a further advanced manufacturing stage, wherein a capacitor
140
is formed in and on the first active region
120
, and a field effect transistor
150
is formed in and on the second active region
130
. The transistor element
150
comprises a gate electrode
133
including, for example, highly doped polysilicon and a metal silicide portion
135
. Moreover, sidewall spacers
134
are formed adjacent to sidewalls of the gate electrode
133
. Source and drain regions
136
, each including a metal silicide portion
135
, are formed in the second active region
130
. The capacitor
140
comprises a conductive portion
123
comprised of the same material as the gate electrode
133
and is formed over the first dielectric layer
121
. The portion
123
represents one electrode of the capacitor
140
. The capacitor electrode
123
includes a metal silicide portion
125
and is enclosed by sidewall spacer elements
124
.
A typical process flow for forming the transistor element
150
and the capacitor
140
may include the following steps. A polysilicon layer may be deposited over the device as shown in
FIG. 1
b
and is patterned by well known photolithography and etching techniques to create the capacitor electrode
123
and the gate electrode
133
. Subsequently, the drain and source region are formed by ion implantation, intermittently the sidewall spacers
134
and the sidewall spacers
124
are formed so that the sidewal spacers
134
may act as implantation masks to appropriately shape the dopant concentration of the drain and

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