Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-05
2004-03-16
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S256000, C438S396000, C438S634000, C438S734000, C438S740000
Reexamination Certificate
active
06706590
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a method of manufacturing a semiconductor device, and more particularly to, a method of manufacturing a semiconductor device capable of preventing plasma-introduced damage of a lower unit device upon a metal contact process for connecting the lower unit device and an upper metal line.
2. Description of the Prior Art
Generally, in a process of manufacturing a semiconductor device, a metal contact process is performed in order to connect a lower unit device and an upper metal line. A plasma dry etch technology for forming a contact hole in the metal contact process includes a main etch process for an etch subject layer and an over-etch process that is performed from the time when the lower conductive layer begins to expose.
FIG. 1
is a cross-sectional view of a semiconductor device for explaining a conventional method of manufacturing the device.
Referring now to
FIG. 1
, a word line
12
is formed on a semiconductor substrate
11
. A first interlayer insulating film
13
of which the surface is planarized is then formed on the word line
12
. Next, a portion of the first interlayer insulating film
13
is etched. A bit line
14
connected to the semiconductor substrate
11
through the etch portion is formed on the first interlayer insulating film
13
. A second interlayer insulating film
15
of which the surface is planarized is formed on the bit line
14
. Thereafter, portions of the first and second interlayer insulating films
13
and
15
are etched. Next, a capacitor
16
connected to the semiconductor substrate
11
through the etched portions is formed on the second interlayer insulating film
15
. A third interlayer insulating film
17
of which the surface is planarized is formed on the capacitor
16
.
The lower unit device is completed by the above process. A metal contact process for connecting the lower unit device and a metal line is then performed.
The metal contact process includes forming a photoresist pattern
18
through which a portion of each of the word line
12
, the semiconductor substrate
11
in the active region, the bit line
14
and the capacitor
16
is opened on the third interlayer insulating film
17
, and then sequentially etching the third, second and first interlayer insulating films
17
,
15
and
13
by means of a plasma dry etch process using the photoresist pattern
18
as an etch mask, thus forming contact holes C
1
, C
2
, C
3
and C
4
.
The plasma dry etch process includes a main etch process for the etch subject layers
17
,
15
and
13
, and an over-etch process that is performed from the time when the lower conductive layers
11
,
12
,
14
and
16
begin to expose. At this time, a word line contact hole C
1
through which a portion of the word line
12
is exposed, a substrate contact hole C
2
through which a portion of the semiconductor substrate
11
in the active region is exposed, a bit line contact hole C
3
through which a portion of the bit line
14
is exposed, and a capacitor contact hole C
4
through which a portion of the capacitor
16
is exposed, are simultaneously formed by the above processes. Each of the word line contact hole C
1
, the substrate contact hole C
2
, the bit line contact hole C
3
and the capacitor contact hole C
4
has a different depth since the lower conductive layers
11
,
12
,
14
and
16
are formed at different locations of the four contact holes C
1
, C
2
, C
3
and C
4
.
In the above, the over-etch process is performed in order to remove the etch subject layers
13
,
15
and
17
that partially remain by a loading effect due to non-uniformity of the process and the difference in the pattern density upon completion of the etch process, a lower step coverage, non-uniformity of composition of the etch subject layer, and the like. The over-etch process time is normally performed as an additional etch process in the range of 30 through 100% based on the process time of the etch subject layers
13
,
15
and
17
. If the thickness of the etch subject layers
13
,
15
and
17
is increased, the thickness of the remnant remained after the etch process is increased. Thus, the over-etch process time is also increased. Due to this, the over-etch process is overly performed in order to completely remove the remnant considering that the lower conductive layers
11
,
12
,
14
and
16
may be damaged by some degree. However, as etching of the etch subject layers
13
,
15
and
17
in the main etch process is already completed, portions through which the lower conductive layers
11
,
12
,
14
and
16
are exposed are additionally etched from the time when the over-etch process begins to expose. Therefore, the characteristic of the device is degraded due to damage of the lower conductive layers
11
,
12
,
14
and
16
, and a phenomenon that an electric charge is accumulated on the surface of the lower conductive layers
11
,
12
,
14
and
16
. In order to minimize damage of the lower conductive layers
11
,
12
,
14
and
16
, the over-etch process is performed under a condition that the etch select ratio for the lower conductive layers
11
,
12
,
14
and
16
is high. In order to minimize degradation in the device characteristic due to accumulation of the electric charge, the over-etch process time is set up so that the over-etch process time is minimized. However, the select ratio that can be obtained in view of the etch process and the over-etch process time that can be reduced are limited.
In case of the substrate contact hole C
2
or the word line contact hole C
1
among the lower conductive layers
11
,
12
,
14
and
16
, the depths of which is deep, there is a case that the surface of the semiconductor substrate
11
in the active region and the word line
12
are not exposed upon the main etch process. In this case, a phenomenon that electric charges are accumulated only on the surface of the insulating material of the etch subject layers
13
,
15
and
17
by plasma is occurred. Therefore, a phenomenon is not generated that the electric charges for the semiconductor substrate
11
or the word line
12
are accumulated. During the over-etch process where the lower conductive layers
11
,
12
,
14
and
16
start to expose, an electric field is formed due to non-uniform accumulation of electric charges through the cross section of the exposed contact. Also, plasma-introduced electric charge current is generated by Fowler-Nordheim tunneling phenomenon by which the underlying substrate becomes a common electrode by the difference in the potential. Due to this, the lower unit device is damaged. Also, plasma-introduced damage is increased in proportion to the time of the over-etch process since it is proportion to the amount of the electric charge accumulated.
Therefore, after the word line, the bit line and the capacitor structure are all formed in the cell region, in order to simultaneously form a metal line for cell driving at a peripheral circuit region, the process of forming a metal contact on the word line, the bit line, and the upper and lower electrodes of the capacitor includes simultaneously etching the contact holes of various depths. Therefore, as the contact holes having a swallow depth like the upper electrode contact of the capacitor is exposed to the over-etch process for a long period of time, plasma-introduced damage is increased.
SUMMARY OF THE INVENTION
The present invention is contrived to solve the above problems and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving an electric characteristic and reliability of the device by reducing plasma-introduced damage of a lower unit device upon a metal contact process for connecting the lower unit device and an upper metal line.
In order to accomplish the above object, a method of manufacturing a semiconductor device according to the present invention, is characterized in that it comprises the steps of forming a word line on a semiconductor substrate and then
Chen Jack
Hynix / Semiconductor Inc.
Jacobson & Holman PLLC
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