Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-06-07
2004-12-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S663000, C438S664000, C438S682000
Reexamination Certificate
active
06835656
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor device manufacturing, and more particularly, to the formation of low resistivity self-aligned silicide regions on the gate and source/drain junctions.
BACKGROUND OF THE INVENTION
There is currently a desire to evaluate the use of selective epitaxial silicon in the manufacturing of semiconductor devices. The need for this technology is the “roadmap” for silicon thickness on silicon-on-insulator (SOI) and the desire for faster parts on bulk silicon. The SOI roadmap suggests that the silicon thickness may be reduced to less than 500 Å in the near future. Assuming that each Angstrom of deposited cobalt (Co) in a conventional salicide process consumes approximately 3.5 Åof silicon from the substrate, a silicon thickness of 500 Å will be mostly consumed by the deposition and reaction of 100-130 Å of Co. Hence, the entirety and even the majority consumption of the silicon will deteriorate the transistor performance significantly. In addition, it is widely accepted that the elevation of the source and drain (or the reduction of silicon consumption) during silicidation is desirable for improving transistor performance, of either bulk or SOI devices.
A major difficulty with elevated source/drain technology is the actual elevating of the source/drains. The process must be selective and uniform, both of which pose difficult challenges. Selectivity means that the silicon must be grown epitaxially upon exposed silicon areas (source and drain), while not depositing on the exposed oxide or nitride regions. In addition, the silicon must be of uniform thickness across the wafer and across areas of differing patterning density. These constraints make the implementation of selective epitaxial silicon difficult. There are additional challenges as well. The process for selective epitaxial silicon involves the in-situ cleaning at elevated temperatures and deposition of silicon from a very reactive precursor. The deposition is sensitive to the condition of the silicon onto which the epitaxial silicon is grown. Thus, any surface damage from reactive chemical etching and/or ion implantation could be catastrophic and a difficult variable to control in the manufacturing of thousands of wafers per week. This makes the implantation of such a technology in actual production very challenging.
There are alternatives to selective epitaxial silicon that are being investigated. Once such technique is described in “A Self-Aligned Silicide Process to Thin Silicon-On-Insulator MOSFETs and bulk MOSFETs with Shallow Junctions”, a manuscript submitted for publication to Materials Research Society (2001), from the IBM T. J. Watson Research Center, Cohen et al. In this alternative technique, Cohen et al. describes the modification of the salicide process to include co-sputtering of silicon with cobalt. After the reaction of this cobalt with the exposed silicon substrate in a conventional salicide process, a layer of amorphous silicon (a-Si) is deposited onto the exposed salicide and reacted with the Co
2
Si during formation of CoSi
2
. The source of silicon above the Co
2
Si helps reduce the silicon consumption from the substrate.
In U.S. Pat. No. 6,165,903, a method is described for forming ultra shallow junctions in a semiconductor wafer with reduced silicon consumption during salicidation by supplying additional silicon during a salicidation process. After the gate and source/drain junctions are formed in a semiconductor device, high resistivity metal silicide regions are formed on the gate and source/drain junctions. Silicon is then deposited in a layer on the high resistivity metal silicide regions. An annealing step is then performed to form low resistivity metal silicide regions on the gate and source/drain junctions. The deposited silicon is a source of silicon that is employed as a diffusion species during the transformation of the high resistivity metal silicide to a low resistivity metal silicide. Since the additional silicon provided in the deposited layer is consumed, there is reduced consumption of the silicon from the ultra-shallow junctions, thereby preventing the bottom of the silicide regions from reaching the bottom of the source/drain junctions.
Although the technique described in U.S. Pat. No. 6,165,903 may be considered a viable alternative to the process of selective epitaxial silicon on production wafers, improvements to the process are desirable in order to produce higher quality devices with reduced expenditures and with higher throughput. This would make the process even more commercially viable.
SUMMARY OF THE INVENTION
These and other needs are met by embodiments of the present invention which provide a method of forming ultra-shallow junctions in a semiconductor wafer, and comprises the steps of forming a gate and source/drain junctions having upper surfaces. First metal silicide regions are formed on the gate and source/drain junctions. These first metal silicide regions have a first resistivity. Amorphous silicon is deposited on the first metal silicide regions. Annealing is performed to form second metal silicide regions with a second resistivity that is lower than the first resistivity. The annealing causes a diffusion reaction of the first metal silicide regions and the amorphous silicon. The depositing of the amorphous silicon and the annealing to form the second metal silicide regions are performed in-situ in a single tool. In certain embodiments of the invention, the single tool is a high density plasma chemical vapor deposition (HDP CVD) tool.
With the present invention, the number of process steps and the number of required tools to produce the structure are reduced. In particular, separate processing tools for deposition of the amorphous silicon and the rapid thermal annealing are not needed. The present invention carries out both functions in a single tool, such as a high density plasma chemical vapor deposition tool, for example. In addition to reducing the number of tools that are used, throughput is increased due to the carrying out of both process steps in a single tool. Also, significant cost savings are also provided, since the high density plasma chemical vapor deposition tool is a relatively inexpensive tool, rather than the relatively expensive processing tools typically employed for depositing amorphous silicon and for performing rapid thermal anneals.
In addition to the cost savings and the higher throughput provided by the present invention, the invention also provides for a uniform deposition of the silicon since it is deposited from a silane precursor and the temperature is well controlled.
In other embodiments of the invention, the earlier stated needs are also met by providing a method of forming silicide, including the steps of forming first metal silicide regions on a substrate, the first metal silicide regions having a first resistivity. Amorphous silicon is then deposited by high density plasma chemical vapor deposition on the first metal silicide regions at a temperature that causes the first metal silicide regions to transform to second metal silicide regions having a second resistivity lower than the first resistivity. At least some of the amorphous silicon is consumed to form the second metal silicide regions.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5994191 (1999-11-01), Xiang et al.
patent: 6165903 (2000-12-01), Besser et al.
patent: 6380040 (2002-04-01), Kepler et al.
patent: 6534402 (2003-03-01), Liao
patent: 6660621 (2003-12-01), Besser et al.
A self-aligned silicide process for thin silicon-on-insulator MOSFETs and MOSFETs with shallow junctions, IBM T. J. Watson Research Center, Yorktown Heights, NY 10598. (a manuscript submitted for publication to Materials Research Society 2001).
Besser Paul R.
Ngo Minh Van
Advanced Micro Devices , Inc.
Le Thao P.
Nelms David
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