Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-03
2004-08-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06775808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to electronic design automation (EDA) tools for designing integrated circuits, and more particularly, the present invention relates to a physical “sign-off” prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design.
2. Description of the Related Art
The use of electronic design automation (EDA) tools has become commonplace for the design of high density integrated circuits. The current design flow used by most integrated circuit design engineers includes the sequential steps of: defining a Register Transfer Level (RTL) description of the circuit; performing logic synthesis which converts the RTL description into a gate level design. The logic synthesis process typically involves several phases. Initially the logic synthesis tool parses and compiles the RTL description into logic equations. Next the logic equations are optimized (i.e., simplified). Finally a gate level net list is generated from the synthesized logic by mapping the logic equations into a gate level design using the cell library, area, power and speed constraints for the process that will be used to fabricate the device; laying out the major functional blocks of the circuit from the net list using a floor planner tool; placing the cells that make up each of the major functional blocks in the circuit using a placement tool; routing the requisite interconnect between the major functional blocks and within the cells using a routing tool; determining the resistive-capacitive delays along all of the interconnect wires using an extraction tool; and performing timing analysis to estimate delays through the cells (transistors) and the propagation delays along each interconnect path (wire) to determine any clock or other timing problems. Based on this analysis, the designer can update or optimize the RTL, synthesis, net list, floor plan, placement and/or routing of the design to correct any problems. A designer will typically perform numerous iterations of the above-defined sequential flow until timing, congestion, and other problems are identified and corrected. When the design has been debugged, then a mask set is generated so the circuit can be fabricated.
The availability of deep sub-micron (0.25 micron and below) processes has enabled high density, system-on-a-chip, designs containing millions and millions of logic gates and transistors that provide rich functionality and high performance. Deep sub-micron processes, however, also pose a problem for design engineers. Optimizing timing is critical for correct operation and high performance, but accurate modeling and estimation of timing for deep sub-micron designs is difficult. A timing value, such as the delay of a critical path, is a function of both the transistors in the cells and the wires that form the interconnect. The delay characteristics of the transistors are specified in the cell library. The delay characteristics of the wires, such as resistance, inductance, and coupling capacitance, are determined by the wire length and other details of the physical design, which is produced by the floor planner, placement, and routing tools. In the current sequential design flow, when the logic synthesis tool attempts to optimize a timing value, the delay through the transistors is available from the cell library, but since the physical design has not been completed (or even started), only crude estimates of the wire lengths and none of the details are available to estimate the delay through the wires. This was not a problem with earlier processes, since the delay of the transistors was the dominant component of timing values and errors in estimating the delay of the wires could be ignored. However, with deep sub-micron processes, interconnect can be the dominant component of timing values, so accurate modeling and estimation is essential. As process technologies advance and designs become ever more complex, creating working, high density circuits running at higher and higher clock rates will become an ever more daunting task for integrated circuit designers.
Current EDA tools are inadequate for deep sub-micron designs. Previous logic synthesis tools are problematic because they generate net lists without sufficient physical layout information. Since wire delays account for such a large proportion of the total delays with deep sub-micron designs, these logic synthesis tools invariably generate sub-optimal net lists. Consequently designers using these tools are often required to perform numerous iterations of the above-defined design sequence, each consuming potentially many weeks or more, before timing problems created from using sub-optimal net lists can be corrected. Since designers usually are under tremendous pressure to complete designs and to quickly bring product to market, these tools are less than adequate in today's competitive environment. Furthermore since these tools are used sequentially and cannot be used simultaneously to resolve problems, some designs may never reach closure.
Therefore a physical “sign-off prototype” tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design is needed.
SUMMARY OF THE INVENTION
The present invention relates to a physical “sign-off” prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design. In either situation, the “sign-off” prototype provides a forward prediction of the area, timing and performance of the final GDS of the design generated by a physical implementation tool. These and other features of the present invention will become apparent upon reading the following detailed descriptions and studying the various figures of the drawings.
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Coudert Olivier R.
Gaitonde Dinesh D.
Gopalakrishnan Padmini
Kreiter Jackson David
Pileggi Lawrence T.
Levin Naum
Monterey Design Systems, Inc.
Siek Vuthe
Vierra Magen Marcus Harmon & DeNiro LLP
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