Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-02-22
2004-12-07
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S635000, C438S706000, C438S738000
Reexamination Certificate
active
06828229
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing an interconnection line in a semiconductor device when using a material having a low dielectric constant in the semiconductor device.
2. Description of the Related Art
In order to overcome reduction in the speed of semiconductor devices due to RC delay between interconnection lines, an attempt to adopt copper (Cu) lines in semiconductor devices has been made. Also, an attempt to use a material having a low dielectric constant for an insulating layer insulating adjacent interconnection lines from each other has been made. In such structures, there is a tendency to pattern interconnection lines made of copper (Cu) by a patterning method known as a dual damascene process.
A variety of approaches are proposed for the dual damascene process and basically include methods of introducing insulating layers formed of double or multi-layers and etching stoppers on the interface or bottom of the insulating layers. When forming trenches, which define the shape of interconnection lines, in the insulating layers, the etching stoppers are introduced to stop the etching process used in forming the trenches.
If the insulating layers used to insulate adjacent interconnection lines from each other are formed of a material having a low dielectric constant as described above, the etch selectivity of the etching stopper with respect to the insulating layers is poor in the etching process used in forming the trenches. The poor etch selectivity of the etching stopper with respect to the material having a low dielectric constant results in over-etching the etching stoppers covering a lower layer during the etching process of forming a via hole and/or a trench in interlayer insulting layers.
For example, an etching stopper covering a lower interconnection line is over-etched during an etching process used in forming a via hole. As a result, the upper surface of the lower interconnection line may be exposed or recessed during a subsequent etching process used in forming a trench. That is, the lower interconnection line is damaged by the dual damascene process.
FIGS. 1 through 5
are cross-sectional views showing the steps of forming an interconnection line by a conventional dual damascene process. Referring to
FIG. 1
, a first etching stopper
40
and a first interlayer insulating layer
50
are sequentially formed over a semiconductor substrate
10
. Here, the first etching stopper
40
covers a lower conductive layer
30
. The lower conductive layer
30
may be a lower interconnection line and is insulated by a lower insulating layer
20
. The lower conductive layer
30
may be electrically connected to an operating device or a transistor formed in the semiconductor substrate
10
. A second etching stopper
45
is formed on the first interlayer insulating layer
50
. A second interlayer insulating layer
55
is formed on the second etching stopper
45
.
Referring to
FIG. 2
, a first etching mask
60
, e.g., a photoresist pattern, is formed on the second interlayer insulating layer
55
. A portion exposed by the first etching mask
60
is etched to form a via hole
71
. Here, it is preferable that an etching process for forming the via hole
71
stops on a portion of the first etching stopper
40
over the lower conductive layer
30
. The first etching mask
60
is then removed.
Referring to
FIG. 3
, a second etching mask
65
, e.g., a photoresist pattern, is formed on the second interlayer insulating layer
55
. A region exposed by the second etching mask is generally wider than the region exposed by the first etching mask
60
.
Referring to
FIG. 4
, a portion of the second interlayer insulating layer
55
exposed by the second etching mask
65
is etched to form a trench
75
which is connected to the via hole
71
. An etching process of patterning the exposed portion of the second interlayer insulating layer
55
to form the trench
75
uses the second etching stopper
45
as an etching stopping point. The etching process of forming the trench
75
is performed after the via hole
71
is formed and thus etches the upper surface of the first etching stopper
40
exposed by the via hole
71
.
Silicon nitride (SiN) or silicon carbide (SiC) used as the first etching stopper
40
may show a poor etch selectivity with respect to the carbon-doped material having a low dielectric constant if the first interlayer insulating layer
50
and/or the second interlayer insulating layer
55
is formed of a material having a lower dielectric constant, e.g., a carbon-doped material having a low dielectric constant such as a carbon-doped silicon oxide (SiOC), to overcome RC delay. Thus, the exposed portion of the first etching stopper
40
may be removed entirely by the etching process of forming the trench
75
by which the upper surface of the lower conductive layer
30
, which must be protected by the first etching stopper
40
, may be exposed.
As described above, the lower interconnection line made of copper (Cu) is damaged if the lower conductive layer
30
, e.g., a lower interconnection line, is exposed to the etching process. Also, after forming the trench
75
, the photoresist pattern used as the second etching mask
65
is removed by ashing and stripping. Ashing is performed using oxygen plasma but the lower interconnection line is greatly recessed or damaged by oxygen plasma if the lower interconnection line is already exposed. Thus, referring to
FIG. 5
, if the lower interconnection line is damaged, when forming an upper conductive layer
80
filling the trench
75
and the via hole
71
, e.g., an upper copper line, poor contact between an upper interconnection line and the lower interconnection line may occur.
Accordingly, as described above, insulating layers, etching stoppers, and a poor etch selectivity resulting from a dual damascene process may cause defective semiconductor devices, e.g., a damaged lower interconnection line.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is an object of the present invention to provide a method of forming an interconnection line in a semiconductor device which can prevent a lower conductive layer from being damaged during a dual damascene process of forming a via hole and a trench.
The invention is directed to a method of forming an interconnection line in a In semiconductor device. In accordance with the method, a first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed. The lower conductive layer or the upper conductive layer may include a copper layer. The first etching stopper and/or the second etching stopper may be formed of silicon nitride or silicon carbide.
The first interlayer insulating layer and/or the second interlayer insulating layer may be formed of a material having a low dielectric constant such as carbon-doped silicon oxide (SiOC).
The protective layer
Kim Jae-hak
Lee Kyoung-woo
Lee Soo-geun
Shin Hong-jae
Mills & Onello LLP
Nguyen Ha Tran
Samsung Electronics Co,. Ltd.
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