Model based metal overetch control

Details Model based metal overetch control Model based metal overetch control

2001-12-12

2004-10-26

Norton, Nadine G. (Department: 1765)

Adhesive bonding and miscellaneous chemical manufacture

Differential fluid etching apparatus

With measuring, sensing, detection or process control means

C156S345250, C156S345260, C156S345330, C156S345510

Reexamination Certificate

active

06808591

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to etching semiconductor devices and in particular to systems and methods utilizing layout data and models for metal overetch control.
BACKGROUND OF THE INVENTION
The use of and demand for semiconductor devices are increasing. Constant development of these devices requires constant improvements in size, performance and yield. These improvements are accomplished by improving the various processes used in semiconductor fabrication. Metal etch processes are often a challenge for sort yield and process control.
One process used in semiconductor fabrication is metalization. Metalization generally involves forming metal layers, interconnects, contacts and plugs. Some metallization processes involve depositing a metal material and performing a chemical mechanical planarization (CMP) process to remove selected portions of the metal material. The CMP process may use CMP endpointing techniques to remove metal material from oxide surfaces without removing too much of the oxide surface.
Other metallization processes involve forming an oxide layer, depositing metal material and removing selected portions of the metal material by etching. An overetch or secondary etch step is then performed to remove remaining metal material and films from oxide surfaces while removing a small amount of the oxide layer. The overetch step avoids a number of problems, such as shorting or bridging, that occur when metal materials are not completely removed from the selected areas. The overetch step intentionally removes a small amount of the oxide layer to ensure that metal is removed from the oxide surface. The etch step is controlled by using an end point detector. However, the overetch step typically can not use an end point detector. Typically, several test wafers are used to characterize oxide loss, wafer profile and overetch process time. For example, several splits of wafers can be used at various percentages of an overetch estimate, such as 10%, 20%, 30% and the like. After the overetch step has been performed, the splits are analyzed to measure oxide loss, profile and the like. This use of test wafers is a time consuming and expensive process.
FIGS. 1A
,
1
B and
1
C illustrate under etch and overetch problems encountered with conventional metal etch processes.
FIG. 1A
illustrates a semiconductor device prior to a conventional metal etch. The semiconductor device comprises a substrate having at least one semiconductor layer
101
, an oxide layer
102
formed on the substrate
101
, a plurality of trenches
105
formed in the oxide layer
102
and a metal layer
104
formed over the oxide layer
102
. The metal layer
104
is comprised of aluminum or an aluminum alloy.
FIG. 1B
illustrates the semiconductor device after a conventional metal etch.
FIG. 1B
illustrates a typical under etch condition. Most of the metal layer
104
has been removed, but a film
106
or small portion of the metal layer
104
remains. The film
106
may cause a multitude of problems, such as bridging.
FIG. 1C
illustrates the semiconductor device after a conventional metal etch.
FIG. 1C
illustrates a typical, undesireable overetch condition. The metal layer
104
has been removed. However, a large amount of the oxide layer
102
has been removed as indicated by the dotted lines
107
. The removed oxide is beyond a tolerable or permissable amount and may render the semiconductor device inoperable.
Therefore, there is an unmet need in the art for new and improved metal overetch control, which reduces costs and more accurately performs overetch processes.
SUMMARY OF THE INVENTION
A system and methodology is provided for facilitating metal overetch control. Metal overetch processes are controlled by utilizing overetch device models.
An overetch system according to one aspect of the invention is disclosed. The overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher.
An overetch system according to one aspect of the invention is disclosed. The overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system. The overetch time controller initiates and halts the metal etcher during overetch processes.
A method of fabricating a semiconductor device according to one aspect of the invention is disclosed. A wafer having at least one semiconductor layer is provided. An oxide layer is formed over the at least one semiconductor layer. A plurality of trenches are formed in the oxide layer. A metal layer is formed over the oxide layer and in the plurality of trenches. A resist layer is deposited over the metal layer. A metal etch is performed to substantially remove the metal layer leaving remaining residue and metal lines in the plurality of trenches. An effective overetch rate is determined for the semiconductor device by utilizing an etch rate model. An overetch endpoint is determined. An overetch is performed according to the overetch endpoint to remove a tolerable amount of the oxide layer and the remaining residue.
A method of fabricating a semiconductor device according to one aspect of the invention is disclosed. A semiconductor device having remaining residue on a first layer is provided. A three dimensional overetch model is used to determine an overetch endpoint. An overetch process is performed according to the overetch endpoint to remove a tolerable amount of the first layer and the remaining residue.
A method of fabricating an overetch control model for a semiconductor device according to one aspect of the invention. A two dimensional layout of the semiconductor device is provided. Information for a third dimension is added. An etchable area is determined. At least one etch rate region is determined. An etch rate is assigned to the at least one etch rate region. The at least one etch rate region and the etchable area are compared to existing overetch models. An acceptable etch rate is calculated.
However, it will be recognized that the invention finds utility in association with semiconductor fabrication generally, and that the invention is thus not limited to any particular embodiment or implementation disclosed and described herein.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.


REFERENCES:
patent: 5780315 (1998-07-01), Chao et al.
patent: 5977542 (1999-11-01), Singh et al.
patent: 6136721 (2000-10-01), Kumihashi et al.
patent: 6322935 (2001-11-01), Smith

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