Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-12
2004-02-10
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000
Reexamination Certificate
active
06689663
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile memory devices and, more particularly, to methods of code programming read-only memory (ROM) semiconductor devices.
2. Description of Related Art
A non-volatile, semiconductor memory device is designed to securely hold data even when power is lost or removed from the memory device. The read-only memory (ROM) is a non-volatile memory device widely used in microprocessor-based digital electronic equipment for storing predetermined programs.
Arrays of memory cells are conventionally disposed in ROM devices for storing data, wherein each memory cell includes a transistor. These transistors, which typically comprise metal-oxide-semiconductor field effect transistors (MOSFETs), are disposed at intersecting bit lines and word lines of the memory device. Data bit values or codes held by these memory cell transistors are permanently stored in the physical or electrical properties of the individual memory cells. Generally speaking, a consequence of the non-volatile nature of a ROM is that data stored in the memory device can only be read.
The fixation of this “read-only” data into the ROM is performed during a code programming process at the original manufacture or fabrication of the memory device. Code programming a ROM typically entails ion implanting the read-only data into transistor channel regions of selected memory cells of the memory.
Since only the channel regions of only selected memory-cell transistors are ion implanted, other areas of the memory device should be covered and protected during the ion-bombardment step. Accordingly, code photomasks have been developed in the prior art for permitting the implantation of ions only into selected regions of the semiconductor. Usage of code photomasks during the code programming process has lead to the characterization of these memory devices as mask ROMs.
Regarding code photomasks, these tools for facilitating code programming of the mask ROM operate using principles of photolithography. Photolithography is a method of transferring a pattern onto a substrate so as to create structures down to the scale of fractions of a micron. A photolithography process can be incorporated, for example, in the fabrication of many modem devices such as MEMS (micro-electro-mechanical systems), optics, and semiconductor devices including mask ROMs.
A typical optical photolithographic process is implemented by depositing onto a substrate such as a semiconductor wafer, by some means (usually a spinner), a layer of photosensitive resist which can be patterned by exposure to ultraviolet (UV) light or another radiation type. To undergo exposure, the photoresist covered wafer is placed beneath a photomask designed to prevent the penetration of radiation through certain portions of the photoresist. Predetermined areas of the photoresist then undergo a degree of polymerization or depolymerization, which can be a function of the nature and extent of photoresist exposure to the radiation. A chemical bath known as a developer can then be used to dissolve parts of the photoresist which remain relatively depolymerized after the radiation by placing the wafer therein and allowing the wafer to be rinsed for a designated time period. Having received the pattern from the photomask, the layer of photoresist on the wafer is typically referred to as a layer of patterned photoresist.
A patterned photoresist layer can be created either on a bare wafer or on a number of previously generated layers of a wafer, with a limitation that the layer or layers should have somewhat planar surfaces to avoid problems including depth of focus variances. Common uses for patterned photoresist include selectively doping certain areas of a wafer while preventing other protected areas from being implanted, and selectively etching underlying layers on a substrate. When used as an implantation barrier, the patterned photoresist can prevent the underlying protected areas from receiving dopant, thereby allowing electrical properties of the substrate to differ between sites. When used as an etch barrier, the patterned photoresist can be functionally unaffected by the etching process, thereby protecting material under the patterned photoresist from being etched.
In certain process steps, it may be beneficial to utilize two consecutively stacked layers of photoresist, with each of the two photoresist layers having a distinct and separate pattern. According to such a construction, certain areas of the substrate can be covered by both photoresist layers, while other areas are covered only partially by a single photoresist layer or not covered at all. When utilizing double photoresist layers, however, a tendency can exist for the first photoresist layer to become softened (depolymerized) during exposure of or to the second photoresist layer. Other problems that may occur with the first photoresist layer include wrinkling due to an additional bake step in connection with processing of the second photoresist layer, loss of dimensional integrity, and the dissolving of portions of the first layer when the substrate is subjected to a developer for the second time. These shortcomings may have the undesirable effect of creating a larger process window and, consequently, may decrease the resolution of the photoresist.
As an alternative solution which may avoid the aforementioned difficulties, prior-art photolithography approaches typically utilize an oxide layer in combination with one or more photoresist layers. For example, an oxide layer can be positioned beneath a second photoresist layer, in place of the first photoresist layer. Implementation of the oxide layer can achieve desired etching and implanting goals in accordance with circuit fabrication objectives without many of the above-discussed problems. Known shortcomings are presented in connection with fabrication processes utilizing oxide layers instead of the first photoresist patterns, as well. For instance, further processing steps are required to pattern the oxide layers, which steps can lead to increased processing times, consumption of additional materials, and augmented costs. Undesirable particles can also be introduced during the oxide deposition and during the oxide patterning process. Furthermore, implementation of an oxide pre-code masking process may induce a critical dimension (CD) bias, and may cause etch uniformity related issues. Imprecise CD control during formation of a pre-code pattern in an oxide layer can adversely affect the real-code implantation process. In the context of mask ROM fabrication and coding, it is desirable to code program the memory devices as quickly and simply as possible, with a minimal expenditure of resources and a minimal risk of adverse particle introduction and CD bias.
A need thus exists in the prior-art for methods of manufacturing mask ROMs in which processing times and materials can be attenuated, to thereby reduce costs. A need also exists for reliable code programming methods which can decrease the potential for particle contamination during the pre-code steps. Furthermore, with device sizes approaching the resolution limit of optical photolithography, wherein, for example, a code implantation area may be 0.15 um
2
, a need continues in the prior-art to exercise precise pre-code and real-code CD control to thereby maintain device performance in a cost effective manner.
SUMMARY OF THE INVENTION
The present invention addresses these needs by providing, in accordance with one aspect, non-volatile memory coding structures and methods for making the same which can be fast, clean, controlled, and simple in construction. The invention disclosed herein provides a method of code programming a mask ROM, wherein a negative photoresist is placed over word lines of the ROM and patterned to thereby form the ROM pre-code pattern directly in the negative photoresist. The negative photoresist is then hardened to enable the forming of a second layer of photoresist directly on the negative photoresist, wherein the sec
Chang Ching-Yu
Yang Ta-Horng
Macronix International Co. Ltd.
Stout, Uxa Buyan & Mullins, LLP
Tsai Jey
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