Process of dual or single damascene utilizing separate...

Details Process of dual or single damascene utilizing separate... Process of dual or single damascene utilizing separate...

2003-12-01

2004-11-23

Nguyen, Van Thu (Department: 2824)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S622000, C438S637000, C438S706000, C438S710000, C438S716000

Reexamination Certificate

active

06821880

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process of dual damascene or damascene, especially to a process with lowered cost and improved reliability.
2. Description of the Related Art
With the increase in integrity of integrated circuits, distances between the metal lines of semiconductor devices are becoming smaller. RC delay caused by the resistance between lines and the capacitance of the dielectric between the lines has become the main reason for delays in signal transmission and limits in device speed. Therefore, copper (Cu) lines and low k materials are continuously being improved for the fabrication of deep sub-micron devices to overcome the increase in parasitic resistance and capacitance caused by narrower line width in advanced process.
Dual damascene process replaces the current Al-Cu metal line process, a process of Back-End of Line (BEOL) of the wafer manufacturing, used after forming the contact plug on the silicon substrate and possibly repeated several times based on the designed number of metal line layers of the device.
Traditional dual damascene process flow can be all-in-one chamber, all-in-one system, or others. As shown in
FIG. 1
a
, all-in-one chamber type uses an all-in-one chamber machine comprising loadlocks
111
, mainframe
113
, and process chamber
112
. Like US 2003/0032278 “All dual damascene oxide etch process steps on one confined plasma chamber”, the all-in-one chamber type accomplishes all dual damascene steps in one chamber. The all-in-one chamber using etching apparatus for ashing has a high Rc failure risk, difficulty in application to low K materials, and low reliability. As shown in
FIG. 1
b
, an all-in-one system type uses an all-in-one system machine comprising loadlocks
121
, mainframe
124
, process chamber
122
, and process chamber
123
. When an all-in-one system type uses etching apparatus for ashing the cost of the process is high, and the process synchronization is poor.
SUMMARY OF THE INVENTION
For this reason, there is a need for a dual damascene process providing good reliability and lower cost.
To achieve this aim, the present invention provides a dual damascene process comprising via/trench etching module, dry cleaning module (DCM), and wet cleaning module. The DCM can include resist ashing, contact ashing, stop layer removal, metal line cleaning, and dielectric layer repair. In the present invention, the via/trench etching and dry cleaning modules are performed in different chambers of different machines. The present invention comprises a via forming and trench forming processes with segments thereof respectively falling into each of the 3 process modules. The via forming process comprises providing an etching apparatus, a DCM machine and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, and a photoresist layer, etching the dielectric layer in the etching apparatus to form a via hole, ashing the photoresist in the DCM machine, and wet cleaning the wafer. The trench forming process comprises providing an etching apparatus, a DCM machine, and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, a contact, and a photoresist layer, etching the dielectric layer and the contact in the etching apparatus to form a trench, ashing the photoresist and the contact in the DCM machine, and wet cleaning the wafer.
The present invention has the advantages of good production capability, lower costs and defects, and extendibility to many low K materials.


REFERENCES:
patent: 6309957 (2001-10-01), Tu et al.
patent: 6500357 (2002-12-01), Luo et al.
patent: 6630406 (2003-10-01), Waldfried et al.
patent: 2003/0032278 (2003-02-01), Chen et al.
patent: 2003/0057179 (2003-03-01), Luo et al.

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