Semiconductor device with high- and low-density regions of...

Details Semiconductor device with high- and low-density regions of... Semiconductor device with high- and low-density regions of...

2000-12-21

2004-12-07

Kang, Donghee (Department: 2811)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S253000, C438S387000, C438S399000

Reexamination Certificate

active

06828188

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having, on a single semiconductor substrate, a high-density region containing transistor elements arrayed at a high density and a low-density region containing transistor elements arrayed at a low density, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
There have heretofore been used semiconductor devices of various structures. For example, semiconductor memories such as DRAMs (Dynamic Random Access Memories) usually have a cell array region as a high-density region and a peripheral circuit region as a low-density region, disposed on a single semiconductor substrate.
The cell array region comprises a two-dimensional high-density array of identical transistor elements that form memory cells, and the peripheral circuit region comprises a low-density array of transistor elements that form various circuits including an XY decoder. In manufacturing such a semiconductor device, the transistor elements in the high-density region and the transistor elements in the low-density region are simultaneously fabricated.
The above conventional semiconductor device and a process of manufacturing the conventional semiconductor device will be described by way of example below with reference to
FIGS. 1 through 7
of the accompanying drawings.
As shown in
FIG. 1
, DRAM
100
has cell array region
102
as a high-density region and peripheral circuit region
103
as a low-density region, disposed on single semiconductor substrate
101
.
Cell array region
102
comprises a high-density array of identical transistor elements
111
that form memory cells
110
, and peripheral circuit region
103
comprises a low-density array of transistor elements
112
that form various circuits including an XY decoder.
Transistor elements
111
,
112
have respective source regions
111
b
,
112
b
and respective drain regions
111
c
,
112
c
formed by introducing an impurity into semiconductor substrate
101
by way of ion implantation. The gaps between source regions
111
b
,
112
b
and drain regions
111
c
,
112
c
function as respective gate regions
111
a
,
112
a
. In cell array region
102
, a pair of adjacent transistor elements
111
sharing source region
111
b
make up memory cell
110
. A plurality of memory cells are arranged in a substantially zigzag pattern (see FIG.
2
). In peripheral circuit region
103
, transistor elements
112
are arranged as desired to form peripheral circuits, though not shown. As a whole, transistor elements
112
in peripheral circuit region
103
are arranged at a density lower than transistor elements
111
in cell array region
102
.
As described above, a plurality of memory cells
110
are arranged in a substantially zigzag pattern as schematically shown in FIG.
2
. The structure of memory cell
110
will briefly be described below. In
FIG. 2
, transistor elements
111
and capacitors
113
in only one of a number of memory cells
110
are denoted by reference numerals.
Gate oxide films
115
are formed on gate regions
111
a
of transistor elements
111
of semiconductor substrate
101
shown in
FIG. 1
, and a plurality of striped gate electrodes
116
, which extend vertically in
FIG. 2
, are disposed at given spaced intervals on the surfaces of gate oxide films
115
. Gate electrodes
116
each comprise two layers including a polysilicon layer
117
and a tungsten silicide layer
118
. Oxide films
119
are formed on the surfaces of gate electrodes
116
. Side walls
120
comprising nitride films are formed on sides of oxide films
119
and gate electrodes
116
.
Central contact electrode
121
is disposed in the gap between side walls
120
over source region
111
b
of transistor element
111
. Outer contact electrodes
122
are disposed in the gaps between side walls
120
over drain regions
111
c
of transistor elements
111
. Therefore, a pair of outer contact electrodes
122
are disposed on both sides of central contact electrode
121
in spaced-apart relation to each other. Outer contact electrodes
122
serve as drain electrodes of transistor elements
111
, and central contact electrode
121
serves as a source electrode of transistor element
111
. One central contact electrode
121
serves as a common source electrode of a pair of transistor elements
111
.
Capacitors
113
are disposed upwardly of central contact electrode
121
and outer contact electrodes
122
and extend outwardly from positions above outer contact electrodes
122
, i.e., remotely from a position above central contact electrode
121
. Essentially, capacitor
113
is of a structure comprising a dielectric sandwiched between a pair of conductors (electrode plates or the like). Specifically, dielectric
113
b
is interposed between conductor
113
a
and conductive bit line
123
. Spherical bodies
113
c
serve to increase the surface area of conductor
113
a.
With the above construction, as seen in plan in
FIG. 2
, a pair of transistor elements
111
are disposed on both sides of source region
111
b
below central contact electrode
121
in sharing relation to source region
111
b
. Capacitors
113
are disposed above positions outside of respective transistor elements
111
. As shown at an enlarged scale in
FIG. 3
, a pair of transistor elements
111
and a pair of capacitors
113
make up a group that serves as a memory cell.
As shown in
FIG. 2
, a plurality of memory cells
110
are arranged in a zigzag pattern, forming a cell array region as a high-density region. Semiconductor substrate
101
has recesses in positions other than transistor elements
111
, and STIs (Shallow Trench Isolations)
114
are disposed in the respective recesses to isolate memory cells
110
from each other. In appropriate positions between memory cells
110
, the electrodes are rendered nonconductive by oxide insulating films
132
shown in
FIG. 1
, thus arranging independent memory cells
110
in the zigzag pattern.
A plurality of striped bit lines
123
, which extend horizontally in
FIG. 2
, are disposed at given spaced intervals above gate electrodes
116
out of direct contact therewith. As shown in
FIG. 1
, bit line
123
has downward extensions
123
a
extending partially downwardly above central contact electrode
121
that is held in contact with downward extension
123
a
. Outer contact electrodes
122
are connected to capacitors
113
disposed thereabove.
In peripheral circuit region
103
, transistor elements
112
comprising gate regions
112
a
, source regions
112
b
, and drain regions
112
c
are formed on semiconductor substrate
101
, substantially as is the case with transistor elements
111
described above. Gate oxide films
115
, gate electrodes
116
which consists of polysilicon layers
117
and tungsten silicide layers
118
, and oxide layers
119
are successively disposed on gate regions
112
a
on the surface of semiconductor substrate
101
. Side walls
120
consisting of nitride films are formed on sides of oxide films
119
and gate electrodes
116
. Downward extensions
123
a
of bit lines
123
are disposed outside of side walls
120
and directly connected to drain regions
112
c
of semiconductor substrate
101
, not via contact electrodes, and function as drain electrodes. Source electrodes (not shown) are connected to source regions
112
b
of semiconductor substrate
101
. In this manner, a path is established for an output signal from a source electrode (not shown) of peripheral circuit region
103
to pass through source region
112
b
, gate region
112
a
, and drain region
112
c
of transistor element
112
, then through bit line
123
and central contact electrode
121
into source region
111
b
of transistor element
111
, and then pass through gate region
111
a
and drain region
111
c
thereof to outer contact electrodes
122
.
A process of manufacturing the semiconductor device, i.e., DRAM
100
described above, will briefly be described below.
STIs
114
are formed in a given pattern in

Affiliated with

Also associated with

Rating

Semiconductor device with high- and low-density regions of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device with high- and low-density regions of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with high- and low-density regions of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3275687