Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-10-22
2004-12-07
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000
Reexamination Certificate
active
06828201
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to dielectrics for field effect semiconductor devices, and more particularly to dielectrics for SONOS-type nonvolatile semiconductor devices.
BACKGROUND OF THE INVENTION
As is well known, semiconductor devices can include an insulated gate field effect transistor (IGFET) type device. IGFET-type devices typically include a transistor gate separated from a channel region by a dielectric. A potential applied to a gate can then be varied to alter channel conductivity.
While many IGFET type devices are volatile (e.g., conventional metal-oxide-semiconductor FETs), nonvolatile devices may also include IGFET-like approaches. One conventional nonvolatile device can be a floating gate electrically erasable programmable read only memory (EEPROM). A floating gate EEPROM can include a floating gate electrode situated between a control gate and a channel. Charge, including electrons and/or “holes” may be stored in a floating gate electrode. Such a charge may alter a threshold voltage of a resulting nonvolatile IGFET-type device. As will be noted below, a drawback to any floating gate device can be higher programming and/or erase voltages with respect to other nonvolatile approaches.
Another nonvolatile IGFET type device can include a dielectric interface to store (i.e., trap) charge. For example, devices have been proposed that include a metal gate formed over a dielectric of silicon nitride and silicon dioxide. Such devices have been referred to as metal-nitride-oxide-semiconductor (MNOS) devices. A drawback to many MNOS devices has been lack of charge retention and/or uniformity of programming.
A third type of nonvolatile device may include one or more dielectric layers for storing charge. Such devices may be referred to generally as silicon-oxide-nitride-oxide-silicon (SONOS) type devices. One very basic type of SONOS device may include a polycrystalline silicon (“polysilicon”) gate formed over a dielectric layer that includes a silicon nitride layer sandwiched between silicon dioxide layers.
SONOS devices can have lower programming voltages than other conventional nonvolatile devices, such as some types of floating gate devices. In addition, the SONOS fabrication process can be compatible with standard complementary metal oxide semiconductor (CMOS) process technology. To maintain this compatibility, SONOS devices may be scaled along with other transistors used in the process. The ability of SONOS devices to maintain performance and reliability as they are scaled can be an important feature.
To better understand the formation of SONOS devices, a conventional way of forming a SONOS device is set forth in
FIGS. 6 and 7
.
FIG. 6
is a flowchart illustrating several process steps involved in creating an integrated circuit containing SONOS devices.
FIGS. 7A-7H
set forth a number of side cross-sectional views of a portion of an integrated circuit containing SONOS devices following the various process steps described in FIG.
6
.
The conventional process described in
FIG. 6
is designated by the general reference character
600
. A conventional process
600
may include the steps of growing a tunnel oxide
602
, depositing a silicon nitride layer
604
, depositing a top oxide layer
606
, depositing a polysilicon gate layer
608
, forming a gate mask
610
, etching gates
612
, and depositing and etching a spacer layer
614
.
Referring to
FIG. 7A
, a side cross-sectional view of a portion of an integrated circuit prior to the beginning of a conventional process
600
is shown. The integrated circuit portion includes a substrate
700
, and may include isolation regions
702
formed by prior process steps. As an example, isolation regions
702
may be formed by various conventional isolation processes including but not limited to shallow trench isolation (STI) or the local oxidation of silicon (LOCOS).
It is noted that a substrate
700
may also include various impurity regions, form by ion implantation and/or diffusion methods. As but a few examples, n-type wells may be formed in a p-type substrate (or vice versa), or p-type wells may be formed within n-type wells (or vice versa). An important aspect of forming diffusion regions can be controlling the depth and/or lateral extents of such regions. Subjecting diffusion regions to temperature cycles following their initial formation can result in the dopants of the diffusion region diffusing deeper and/or further than desired, increasing the extents of the junction, and/or lowering the “abruptness” of a dopant concentration at the edge of a p-n junction. Too many temperature cycles may thus result in adverse transistor operation due to junction breakdown or “punchthrough” current, to name just two examples. Consequently, the fabrication process of an integrated circuit may emphasize minimizing a device's exposure to temperature cycles (keeping as small a “thermal budget” as possible).
Referring again to
FIG. 6
, a conventional process
600
may begin by growing a tunnel oxide (step
602
). A portion of an integrated circuit following step
602
is set forth in FIG.
7
B. Referring to
FIG. 7B
, a portion of an integrated circuit includes a tunnel oxide
704
on a substrate
700
. A tunnel oxide
704
is generally very thin and may be on the order of 15 angstroms (15 Å) thick.
A conventional process
600
can continue by depositing a silicon nitride layer (step
604
). A portion of an integrated circuit following step
604
is set forth in FIG.
7
C. Referring to
FIG. 7C
, an integrated circuit portion now includes a nitride layer
706
deposited over a tunnel oxide
704
. A nitride layer
706
generally consists of silicon nitride (Si
3
N
4
), and may be 80-100 Å thick.
A conventional process
600
can continue by depositing a top oxide layer (step
606
). Referring to
FIG. 7D
, an example of a portion of an integrated circuit following step
606
is set forth. A substrate
700
now includes a tunnel oxide
704
, a nitride layer
706
and a top oxide layer
708
. A top oxide layer
708
can be conventionally formed by chemical vapor deposition (CVD) and may generally be 30-40 Å thick.
A conventional process
600
can continue by depositing a polysilicon gate layer (step
608
). An example of a portion of an integrated circuit following step
608
is set forth in FIG.
7
E. Referring to
FIG. 7E
, a polysilicon gate layer
710
has been deposited on a top oxide layer
708
. As also shown in
FIG. 7E
, a gate protection insulator may also be formed over polysilicon gate layer
710
.
At this point, in the conventional process
600
, five layers of a SONOS device have been created. The silicon-oxide-nitride-oxide-silicon layers correspond to the substrate
700
, tunnel oxide layer
704
, nitride layer
706
, top oxide layer
708
, and polysilicon gate layer
710
, respectively.
The conventional process
600
may continue with lithography and etch steps to isolate and form SONOS devices. A gate mask may first be formed (step
610
). An example of a portion of an integrated circuit following step
610
is set forth in
FIG. 7F. A
gate mask material
712
has been deposited and patterned using any of various lithographic techniques. The gate mask material
712
may generally consist of a photoresist material.
Following the formation of a gate mask (step
610
), gates can be etched (step
612
). Referring to
FIG. 7G
, a portion of an integrated circuit following step
612
is set forth. A suitable etch process has been applied to remove portions of the tunnel oxide
704
, nitride layer
706
, top oxide layer
708
, and polysilicon gate layer
710
that are not covered by gate mask material
712
. In this manner, SONOS devices are formed and isolated on the substrate
700
.
The conventional process
600
can continue by depositing and etching a spacer layer (step
614
). An example of a portion of an integrated circuit following step
614
is set forth in FIG.
7
H. Referring to
FIG. 7H
, a spacer layer
714
has been formed that surrounds and isolates the SONOS gate
Cypress Semiconductor Corporation
Kilday Lisa
Pert Evan
Sako Bradley T.
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