Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-03-25
2004-04-20
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S309000
Reexamination Certificate
active
06723592
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating an image sensor. More particularly, the present invention relates to a method of fabricating an X-ray detector array including a plurality of pixels, each including a storage capacitor and a thin film transistor (TFT).
2. Description of the Background Art
Electronic matrix arrays find considerable application in X-ray image sensors. Such devices generally include X and Y (or row and column) address lines transversely and longitudinally spaced apart and across at an angle to one another, thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. a pixel) to be selectively addressed. These elements in many instances are memory cells or pixels of an electronically adjustable memory array or X-ray imaging array.
Typically, at least one switching or isolation device such as a diode or thin film transistor (TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the TFTs and diodes act as switching elements for energizing or otherwise addressing corresponding memory cells or storage capacitors.
In
FIG. 1
, a background X-ray detector for capturing digital radiographic images is illustrated. The X-ray detector includes a plurality of pixels
3
, each including a thin film transistor (TFT)
5
and a storage capacitor
7
. The storage capacitor
7
in each pixel includes a charge collector electrode
4
that functions as a top plate of the storage capacitor, and a pixel electrode
11
that functions as a bottom electrode of the capacitor.
FIG. 2
is a top view of a background X-ray detector pixel.
FIG. 2B
is a sectional view taken along line C-C′ of FIG.
2
A. As shown in
FIGS. 2A and 2B
, each pixel of the background art includes a substrate
200
, a gate electrode
205
, a gate line
206
, a first gate insulation layer
210
, an a-Si layer
215
, an &agr;-Si (amorphous silicon) layer
215
, an n
+
&agr;-Si layer
220
, a common line
225
, a source electrode
230
, a drain electrode
235
, a data line
240
, a planarization layer
245
, a first via hole
250
, a second via hole
255
, a bottom electrode (a pixel electrode)
260
, a dielectric layer
265
, and a top electrode (a charge collector electrode)
270
. In addition, symbol Cs indicates a storage capacitor.
The method for fabricating the above X-ray detector includes seven steps of photolithography and etching. That is, the background method requires seven masks. The processing steps are concisely described as follows.
The first photolithography step defines the gate electrode
205
and the gate line
206
.
The second photolithography step defines the &agr;-Si layer
215
and the n
+
&agr;-Si layer
220
to obtain a semiconductor island structure.
The third photolithography step defines the common line
225
, the source electrode
230
, the drain electrode
235
, and the data line
240
.
The fourth photolithography step defines the first via hole
250
.
The fifth photolithography step defines the bottom electrode (the pixel electrode)
260
.
The sixth photolithography step defines the second via hole
255
.
The seventh photolithography step defines the top electrode (the charge collector electrode)
270
.
SUMMARY OF THE INVENTION
The inventors of the present invention have recognized that to decrease manufacturing costs, a method that requires utilizing fewer masks than in the background method would be beneficial.
Thereby, an object of the present invention is to provide a novel method of fabricating an X-ray detector array element.
Another object of the present invention is to provide a novel method of fabricating an X-ray detector array element, requiring only six masks during photolithography.
In order to achieve these objects, the present invention provides a novel method of fabricating an X-ray detector array element. A substrate having a capacitor area and a transistor area is provided. A transversely extending gate line is formed on the substrate, wherein the gate line includes a gate electrode in the transistor area. A gate insulation layer is formed on the gate line, the gate electrode, and the substrate. A semiconducting island is formed on the gate insulation layer in the transistor area. A longitudinally extending common line and a longitudinally extending data line are formed on the gate insulation layer, and simultaneously, a source electrode and a drain electrode are formed on the semiconducting island to form a thin film transistor (TFT) structure, wherein the drain electrode electrically connects to the data line. A planarization layer is formed on the gate insulation layer, the common line, the TFT structure, the data line, and the gate line. A first conductive layer is formed on the planarization layer in the capacitor area. A dielectric layer is formed on the first conductive layer and the planarization layer. A first via hole and a second via hole penetrating the dielectric layer and the planarization layer are formed, wherein the first via hole exposes the surface of the source electrode, and the second via hole exposes part of the surface of the first conductive layer and part of the surface of the common line. A conformal second conductive layer is formed on the dielectric layer, the interior surrounding surface of the first via hole, and the interior surrounding surface of the first via hole. Part of the second conductive layer is removed to form a third conductive layer, a fourth conductive layer, and a first opening. The third conductive layer is isolated from the fourth conductive layer by the first opening, the third conductive layer electrically connects to the source electrode, and the first conductive layer electrically connects to the common line by the fourth conductive layer. Thus, a storage capacitor structure composed of the first conductive layer, the dielectric layer, and the third conductive layer in the capacitor area is obtained.
The present invention also provides another method of fabricating an X-ray detector array element. A substrate having a capacitor area and a transistor area is provided. A transversely extending gate line is formed on the substrate, wherein the gate line includes a gate electrode in the transistor area. A gate insulation layer is formed on the gate line, the gate electrode, and the substrate. A semiconducting island is formed on the gate insulation layer in the transistor area. A longitudinally extending common line and a longitudinally extending data line are formed on the gate insulation layer, and simultaneously, a source electrode and a drain electrode are formed on the semiconducting island to form a thin film transistor (TFT) structure, wherein the drain electrode electrically connects the data line. A planarization layer is formed on the gate insulation layer, the common line, the TFT structure, the data line, and the gate line. A first conductive layer having a first opening is formed on the planarization layer in the capacitor area, wherein the first opening exposes the planarization layer above the common line. A dielectric layer is formed on the first conductive layer and the planarization layer. A first via hole and a second via hole penetrating the dielectric layer and the planarization layer are formed. The first via hole exposes the surface of the source electrode, the second via hole exposes part of the surface of the first conductive layer and part of the surface of the common line, and the second via hole and the first opening overlap. A conformal second conductive layer is formed on the dielectric layer, the interior surrounding surface of the first via hole, and the interior surrounding surface of the second via hole. Part of the second conductive layer is removed to form a third conductive layer, a fourth conductive layer, and a second opening. The third conductive layer is isolated f
Hannstar Display Corporation
Nhu David
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