Electrical computers and digital processing systems: memory – Storage accessing and control
Patent
1996-07-15
1998-10-13
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
711154, 395821, G06F 1200, G06F 1300
Patent
active
058227520
ABSTRACT:
The present invention is related to a circuit useful to manage a random order queue having a plurality of queue entries, each queue entry having an associated validity bit which indicates whether the queue entry contains valid data. In one embodiment, the circuit includes a first plurality of inputs for receiving validity signals responsive to a first group of validity bits, a second plurality of inputs for receiving shift signals responsive to a second group of validity bits, and a plurality of outputs for providing select signals to multiplexers coupled to the queue, the select signals being responsive to the shift signals and the validity signals.
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patent: 3629857 (1971-12-01), Faber
patent: 4507760 (1985-03-01), Fraser
patent: 5327557 (1994-07-01), Emmond
patent: 5359709 (1994-10-01), Blanc et al.
patent: 5638538 (1997-06-01), VanDoren et al.
patent: 5664114 (1997-09-01), Krech, Jr. et al.
Cheong Hoichi
Ciraula Michael Kevin
Le Hung Qui
Muhich John Stephen
England Anthony V. S.
International Business Machines - Corporation
Swann Tod R.
Thai Tuan V.
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