Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-07-12
2004-04-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S073100
Reexamination Certificate
active
06721913
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an interface testing circuit and method for testing an interface between two or more separate hardware components, such as between a read/write (R/W) module and a hard disk controller (HDC), fabricated on an integrated circuit.
BACKGROUND OF THE INVENTION
Testing of digital circuits at the chip, board, or system level is done, for example, to detect the presence of hardware failures caused by faults in the manufacturing processes. The behavior of a digital system is characterized by discrete responses to discrete operating state/input signal permutations, such that testing of a digital circuit may be achieved by checking its behavior under every operating mode and input signal permutation. While this approach is valid in principle, most digital circuits are too complex to be tested using such an exhaustive technique. Instead testing methods and tools have been developed to test digital circuits using only a fraction of all possible test conditions.
Such conventional hardware testing tools check internal gates within a hardware block. These tools generate vectors to test the inputs and outputs of the gates. However, a disadvantage of these tools is that they are not designed to test the interface between two hardware components. Furthermore, testing between two blocks may not be possible with conventional tools due to mixed signal (e.g., analog and digital) components.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an interface testing system for testing an interface between two or more separate hardware components, such as between a hard disk controller (HDC) and read/write (R/W) module.
It is another object of this invention to provide such an interface testing system which does not require complex and expensive synchronized mixed signal testing between the hardware components.
According to one aspect of the invention, an interface testing circuit for testing an interface between a plurality of hardware components fabricated on an integrated circuit is provided. The interface testing circuit comprises one or more test input/output pads; a first sub-circuit, in communication with a test input/output pad, that is adapted to route a first test signal from that test input/output pad to one of the hardware components, or to route a first output signal from another one of the hardware components to that test input/output pad; and a second sub-circuit, in communication with a test input/output pad, that is adapted to route a second test signal from that test input/output pad to one of the hardware components, or to route a second output signal from another one of the hardware components to that test input/output pad.
In one embodiment, the first sub-circuit of the interface testing circuit routes the first test signal from the corresponding test input/output pad to a first hardware component, and the second sub-circuit routes the second output signal from the first hardware component to the corresponding test input/output pad.
Preferably, the first sub-circuit comprises a first multiplexer in communication with the corresponding test input/output pad, and a first AND gate in communication with the first multiplexer and that test input/output pad; and the second sub-circuit comprises a second multiplexer in communication with the corresponding test input/output pad, and a second AND gate in communication with the second multiplexer and that test input/output pad.
In one embodiment, the interface testing circuit comprises a single test input/output pad that the sub-circuits share. In another embodiment, each sub-circuit has its own test input/output pad.
In a preferred embodiment, the first multiplexer has a first input that receives the first test signal, a second input that receives the first output signal, and an output, the first multiplexer being responsive to a first select signal to select either the first test signal or the first output signal as the output of the first multiplexer, and the second multiplexer has a first input that receives the second test signal, a second input that receives the second output signal, and an output, the second multiplexer being responsive to a second select signal to select either the second test signal or the second output signal as the output of the second multiplexer.
Preferably, the first AND gate has a first input in communication with the output of the first multiplexer, a second input that receives the second select signal, and an output in communication with the corresponding test input/output pad, and the second AND gate has a first input in communication with the output of the second multiplexer, a second input that receives the first select signal, and an output in communication with the corresponding test input/output pad.
Another aspect of the invention involves a method for testing an interface between a plurality of hardware components fabricated on an integrated circuit. The method comprises the steps of (a) routing either a first test signal from a test input/output pad to one of the hardware components, or a first output signal from another one of the hardware components to the test input/output pad; and (b) routing either a second test signal from the test input/output pad to one of the hardware components, or a second output signal from another one of the hardware components to the test input/output pad.
In one embodiment step (a) comprises the step of routing the first test signal from the test input/output pad to a first hardware component, and step (b) comprises the step of routing the second output signal from the first hardware component to the test input/output pad.
In a preferred embodiment step (a) comprises the steps of (a)(
1
) receiving the first test signal, (a)(
2
) receiving the first output signal, and (a)(
3
) selecting, in response to a first select signal, either the first test signal or the first output signal, and step (b) comprises the steps of (b)(
1
) receiving the second test signal, (b)(
2
) receiving the second output signal, and (b)(
3
) selecting, in response to a second select signal, either the second test signal or the second output signal.
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patent: 6560734 (2003-05-01), Whetsel
Abraham Esaw
De'cady Albert
Marvell International Ltd.
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