Method of patterning capacitors and capacitors made thereby

Details Method of patterning capacitors and capacitors made thereby Method of patterning capacitors and capacitors made thereby

2002-09-27

2004-05-11

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06734057

ABSTRACT:

The present invention relates to a method of patterning capacitors, especially for ferroelectric applications including non-volatile memories known as FeRAM and for high-k dynamic random access memory (DRAM).
Ferroelectric capacitors have the advantage that they are able to switch quickly and can be fabricated on a single VLSI chip.
FeRAM's are advantageous in that they have the endurance of DRAM, the fast read/write times of SRAM and the non-volatility of flash.
Conventionally, an FeRAM is manufactured by depositing a ferroelectric film, such as lead zirconate titanate (PZT) or strontium ruthenium oxide (SRO) on a first, planar, electrode film, and forming a second electrode film over the ferroelectric layer. The second electrode layer and the ferroelectric film are then etched using a reactive ion etch method, after which the first electrode film is etched using a similar method. The result is a number of stacks comprising a first and second electrode film sandwiching the ferroelectric film.
Such a manufacturing method has various disadvantages. Firstly, due to the low etch rate of the ferroelectric film, the devices are slow to manufacture and this results in a low productivity. Secondly, as a result of the poor selectivity of the etch mask, the etching has a low taper angle. This reduces the density of capacitors that may be formed on the device, and therefore limits the capacity of a memory formed using the technique.
According to a first aspect of the present invention, a method of forming a capacitor includes the steps of:
providing a first layer,
patterning the first layer:
forming a second layer on the first layer, the second layer being formed of a ferroelectric material, the ferroelectric material having a morphology dependent upon the underlying first layer;
patterning the second layer; and,
forming a conductive layer over the resulting structure.
With the method according to the present invention, the patterning of the second, ferroelectric layer, will be dependent upon the morphology of the layer, which is in turn dependent upon the patterning of the underlying, first layer. Therefore, by patterning the first layer prior to forming the ferroelectric layer, the patterning of the ferroelectric layer may advantageously be affected. In particular, where the ferroelectric layer is formed over a portion where the first layer remains, the ferroelectric layer may have a crystalline morphology, however where the ferroelectric layer is deposited over a portion where the first layer has been removed, the ferroelectric layer may have an amorphous morphology. Since the patterning of the ferroelectric layer is dependent upon the morphology of the ferroelectric layer, the patterning will be different in different regions dependent upon the patterning of the underlying layer.
The patterning of the first layer may be carried out by a reactive Ion etching (RIE) method. Such a method for etching electrically conductive and electrically insulating materials is well known.
The patterning of the ferroelectric layer is preferably carried out by a reactive ion etch or a wet etching method. For both methods, the rate of etching of ferroelectric material is much greater for amorphous material than for crystalline material. For example, for PZT, the etch rate for amorphous PZT by a reactive ion etching method is about four times that for crystalline PZT, and for etching using a wet etching method, the etch rate for amorphous PZT is about nine times that for amorphous PZT. Therefore, by patterning the underlying first layer, to selectively control the morphology of the ferroelectric layer, the time required for etching of the ferroelectric layer may be reduced. A further advantage of the present invention is that the selective etching of a ferroelectric layer by selective reactive ion etching is that no mask is required. This is advantageous as it avoids the cost and time associated with producing such a mask. Furthermore, the etching is able to create a steeper taper angle than is possible with the use of a mask. This allows a greater density of capacitors to be formed.
In one embodiment, the first layer is formed of an electrically conductive material, such as Pt, Ir. IrO
2
or SRO. Where the first layer is formed of an electrically conductive material, this layer may form a first electrode with the conductive layer deposited over the ferroelectric layer forming a second electrode.
In an alternative embodiment, the first layer is formed of a generally non-electrically conductive material, such as Al
2
O
3
, SiN or SiO
2
. In this case, it is preferred that the electrically conductive layer deposited over the ferroelectric layer functions as both electrodes.
According to a second aspect of the present Invention, there is provided a capacitor formed in accordance with the method of the first aspect of the present invention.


REFERENCES:
patent: 5070026 (1991-12-01), Greenwald et al.
patent: 5759265 (1998-06-01), Nashimoto et al.
patent: 5889299 (1999-03-01), Abe et al.

Affiliated with

Also associated with

Rating

Method of patterning capacitors and capacitors made thereby does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of patterning capacitors and capacitors made thereby, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of patterning capacitors and capacitors made thereby will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3262183