Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-10
2004-05-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S231000, C438S232000, C438S237000, C438S201000, C438S203000, C438S207000, C257S588000, C257S577000, C257S627000
Reexamination Certificate
active
06730557
ABSTRACT:
RELATED APPLICATION DATA
The present invention claims priority to Japanese Application No. P2000-210259 filed Jul. 11, 2000, which application is incorporated herein by reference to the extent permitted by law.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device consisting of bipolar transistors and to a process for producing the same.
There is a semiconductor device called BiCMOS which consists of bipolar transistors and CMOS transistors formed on a common substrate. It displays high performance by virtue of the former's accurate analog processing ability and high-speed operation and the latter's high integration and low power consumption.
In the case where the MOS transistor is that of LDD (Lightly Doped Drain) structure, the gate electrode has side walls formed on its flanks, the LDD region is formed by introducing an impurity with the help of the gate electrode as a mask, and the source/drain regions are formed by introducing an impurity with the help of the gate electrode and side walls as a mask.
Incidentally, the LDD structure is characterized in that the MOS transistor has in its drain region a lightly doped region which permits the gate length to be reduced while relieving the electric field effect resulting from the reduced gate length.
In the case of the above-mentioned BiCMOS semiconductor device, the LDD structure can be formed in the same way as above if the MOS transistor has the LDD structure.
An example of the BiCMOS semiconductor device is explained in the following with reference to
FIGS. 16A and 16B
which are schematic sectional views showing its structure that is observed after side walls have been formed in its manufacturing process.
FIG. 16A
is a schematic sectional view showing a PMOS transistor, an NMOS transistor, and a vertical NPN bipolar transistor (NPN transistor for short hereinafter).
FIG. 16B
is a schematic sectional view showing a lateral PNP transistor (LPNP transistor for short hereinafter).
As shown in
FIGS. 16A and 16B
, the BiCMOS semiconductor device consists of a PMOS transistor
101
, an NMOS transistor
102
, an NPN transistor
103
, and an LPNP transistor
104
.
On the P-type semiconductor substrate
111
is formed an N
+
buried region
112
for the PMOS transistor
101
, the NPN transistor
103
, and the LPNP transistor
104
. On the semiconductor substrate
111
is formed also an N-type epitaxial layer
113
. These components constitute the semiconductor base
110
.
On the surface of the semiconductor base
110
is formed an element isolating layer
115
by LOCOS, so that elements are isolated from one another.
Further, there is also formed a heavily doped N-type region
116
for connection to the collector of the NPN transistor
103
and the base of the LPNP transistor
104
.
In the PMOS transistor
101
is formed an N-type semiconductor well region
117
. In the NMOS transistor
102
is formed a P-type impurity region
118
which functions as both a P-type semiconductor well region
118
W and a channel stop region
118
C for the bipolar transistor.
On the semiconductor base
110
is formed a gate oxide film
119
for each of the PMOS and NMOS transistors
101
and
102
. On the gate oxide film
119
is formed a gate electrode G of tungsten polycide which consists of an N-type polysilicon film
120
and a tungsten film
121
.
The P-type LDD regions
124
are formed in those parts of the N-type semiconductor region
117
which are adjacent to both sides of the gate electrode G of the PMOS transistor
101
.
Likewise, LDD regions
125
are formed in the NMOS transistor
102
.
In addition, the gate electrode G in each of the PMOS and NMOS transistors
101
and
102
has on its flanks insulating side walls
128
which determine the width of the LDD regions
124
and
125
.
These side walls
128
are formed by coating the entire surface with an insulating film and then performing reactive ion etching (RIE) on this insulating film.
When this reactive ion etching is carried out to form the side wall
128
, the epitaxial layer
113
which is silicon is exposed except for those parts covered by the element isolating layer
115
and the polysilicon region (or gate electrode G). Therefore, RIE causes damage to the silicon.
The problem arises in the process of producing silicon semiconductor devices having MOS transistors.
In the case of MOS transistor, that region of the epitaxial layer (silicon) which exposes itself when the side walls are formed is the source/drain region.
The source/drain region is a heavily doped region and hence it affects only a little the transistor characteristics even though it is damaged by RIE.
However, in the case of BiCMOS semiconductor device shown in
FIGS. 16A and 16B
, damages due to RIE greatly affect the transistor characteristics because the bipolar transistors
103
and
104
are formed in the region where silicon exposes itself. This holds true particularly with the lateral bipolar transistor
104
formed near the surface of the semiconductor base. The result of damage is an increase in surface recombination current which in turn decreases the current amplification factor (h
FE
) at low current, and this leads to poor reliability.
Therefore, it is important for the BiCMOS semiconductor device that the bipolar transistor, particularly its active region, should not be damaged by RIE.
In the meantime, a lateral bipolar transistor is formed in such a way that regions for the emitter, base, and collector spread out laterally. Consequently, it takes a larger area than a vertical bipolar transistor.
It is desirable to reduce the area for lateral bipolar transistors in order to increase the degree of integration of semiconductor devices.
SUMMARY OF THE INVENTION
The present invention was completed in view of the foregoing. It is an object of the present invention to provide a semiconductor device consisting of lateral bipolar transistors capable of high integration.
It is another object of the present invention to provide a semiconductor device consisting of lateral bipolar transistors with good characteristic properties and to provide a process for producing the semiconductor device.
The present invention is directed to a semiconductor device having lateral bipolar transistors formed on the semiconductor base, characterized in that an opening is formed in the insulating film on the semiconductor base at the base connecting part of the lateral bipolar transistor and an electrode of the base connecting part is formed such that it connects to the semiconductor base through the opening and it covers the base region between the emitter and the collector.
The semiconductor device of the present invention constructed as mentioned above offers the advantage that the base connecting part is formed on the region between the emitter and the collector. This structure makes it possible to reduce the cell size of the lateral bipolar transistor and to reduce the parasitic capacity.
In addition, the semiconductor device constructed as mentioned above offers the advantage that the emitter region and collector region can be formed on both sides of the base region by the self-alignment process that utilizes the electrode layer of the base connecting part. In other words, the base width is determined by self-alignment, and this leads to stable characteristics Moreover, self-alignment makes it possible to form the emitter region, base region, and collector region close to one another, and this helps reduce the cell size.
The present invention is directed also to a semiconductor device which is characterized in that lateral bipolar transistors and MOS transistors are formed on a common semiconductor base and side walls on the gate electrode of the MOS transistor and insulating film covering the base region of the base connecting part of the lateral bipolar transistor are formed with a common insulating film.
The advantage of the semiconductor device constructed as mentioned above is that the insulating film that covers the base region of the base connecting part of the lateral b
Anya Igwe U
Depke Robert J.
Holland & Knight LLP
Smith Matthew
Sony Corporation
LandOfFree
Semiconductor device and production thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and production thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and production thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3255704