Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2002-05-14
2004-01-20
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C327S202000
Reexamination Certificate
active
06680622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention is generally related to registers having serial scan capabilities and, in particular, to selectively disabling a scan output of flip-flops forming the registers.
2. Description of Related Art
Testing of integrated circuits has become a vital operation during the manufacturing, packaging, and the active life of the integrated circuits. However, due to the complexity of integrated circuits and the implementation of the integrated circuits using Very Large Scale Integration (VLSI) processing, the accessibility of every node within the integrated circuit has become difficult and almost impossible without employment of suitable design for test techniques.
A number of design for test (DFT) techniques exist which improve the controllability and/or observability of the internal nodes within an integrated circuit (IC) chip. One known DFT technique for synchronous digital integrated circuits is a serial scan test technique. According to the serial scan test technique, the integrated circuit chip is selectively configured into a test mode of operation wherein the registers in the integrated circuit chip are configured as at least one serial shift register chain having an input and an output externally accessible from outside the integrated circuit chip. In general terms, a test input signal pattern is shifted in the serial shift register chain, the registers are then configured into a normal mode of operation, one or more clock pulses occur, the registers are reconfigured in the test mode of operation, and the new values stored in the registers are shifted out of the serial shift register while a new test input signal pattern is shifted therein. The scan output of the serial shift register is monitored and compared to expected data. These steps are repeated until a desired fault coverage level of the IC chip has occurred.
Conventional register flip-flops include a clock input, at least one data input, and at least one data output. Conventional register flip-flips having serial scan capability may include a scan input, a scan output, and a test enable input which are utilized in the testing operation. The scan output of the flip-flop typically follows the data output or the logical inverse thereof This is acceptable when the flip-flop is configured in the test mode of operation. However, when in the normal mode of operation, the scan output is not typically used and thus will needlessly dissipate power when following the data output signal. Moreover, the scan output will undesirably generate noise when toggling between logic states, which may affect others components and signals in the integrated circuit chip. Based on the foregoing, there is a need for an improved register flip-flop having serial scan capabilities.
SUMMARY OF THE INVENTION
The present invention describes an integrated circuit that is configured to operate in a normal mode of operation and a test mode of operation. The registers within the integrated circuit form a serial shift register chain when in the test mode of operation. The registers contain therein flip-flops, each of the flip-flops having at least one data input, a scan test input, a data output, and a scan output. The flip-flop is capable of storing either the signal appearing on the at least one data input or the signal appearing on the scan test input, based on the mode of operation of the flip-flop. The flip-flop includes a circuit coupled between the data output and the scan output for selectively disabling the scan output from following the value of the data output. Consequently, the scan output is enabled to output the logic value stored in the flip-flop when the flip-flop is in the test mode of operation and is disabled from outputting the logic value stored in the flip-flop when the flip-flop is in the normal mode of operation. When the scan output is disabled from following the data output, the scan output is driven to a predetermined logic value. Thus, by disabling the scan output from following the value of the data output during the normal mode of operation and causing the scan output to be at a fixed logic level, the power dissipation caused by the unnecessary toggling of the scan output is substantially eliminated and the noise produced in the integrated circuit chip is reduced.
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patent: 5444404 (1995-08-01), Ebzery
patent: 5668490 (1997-09-01), Mitra et al.
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Cho James H.
Szuwalski Andre
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