Non-volatile memory cell and fabrication method

Details Non-volatile memory cell and fabrication method Non-volatile memory cell and fabrication method

2002-07-22

2004-05-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06734063

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention lies in the field of electrically writable and erasable non-volatile flash memories comprising NROM-type memory cells preferably arranged in a virtual-ground NOR array.
Extremely small non-volatile memory cells are required for very large-scale integration densities in multimedia applications. However, while the minimum feature size, which is determined by lithography, continues to decrease, other parameters can no longer be scaled accordingly.
NROM-type memory cells are described in B. Eitan et al., “NROM: A novel localized trapping, 2-Bit nonvolatile memory cell”, IEEE Electron Device Letters 21, 543-545 (2000). Currently, NROM cells are fabricated as planar-type MOS transistors using a triple layer of oxide-nitride-oxide both as gate dielectric and as memory or programming layer. The intermediate nitride layer is used as a storage layer for trapping charge carriers, preferably electrons. Due to the specific properties of the used materials, typical source/drain voltages of 4 V to 5 V are necessary during program and erase operations.
At these comparatively high voltages, a punch-through occurs that impedes further scaling down of transistor channel lengths to values below 200 nm. Punching is supposed to take place between the n
+
-junctions of the source/drain regions through the semiconductor material below the channel region. Recent research in the physics of semiconductor devices demonstrated a superior punching behavior as well as an improvement of short channel properties when the channel is confined below by a buried oxide layer at a certain distance from the gate electrode.
MOSFETs on SOI substrates are described in the book by Jean-Pierre Colinge, “Silicon-on-insulator Technology: Materials to VLSI”, 2
nd
ed., Kluwer Academic Publishers, Dordrecht 1997, Chapter 5: “The SOI MOSFET”. The vertical extension of the channel region of SOI MOSFETs is limited by the insulating layer of the SOI substrate. The channel is partially or fully depleted, depending on the thickness of the channel region, which determines, inter alia, whether the space-charge regions adjacent to the gate-oxide and adjacent to the insulating layer are separated or join each other. The SOI MOSFET is completely electrically insulated towards the bulk substrate, unless there is a via provided through the insulating layer so that the bulk substrate can be electrically contacted from the upper surface.
At the 3
rd
European Workshop on Ultimate Integration of Silicon (ULIS 2002), Munich 2002, Thomas Skotnicki presented a NANO CMOS with 16 nm gate length. This type of transistor structure provides a backside channel isolation that is essentially confined to the channel region and is formed by removing an about 15 nm thick epitaxially grown SiGe layer and substituting it with electrically insulating material. The vertical dimension of the undoped and fully depleted channel is comparable to state of the art SOI MOSFETs. The heavily doped source and drain regions extend below the insulating layer level and are provided with LDD (lightly doped drain) regions as channel junctions. The channel structure is called SON, Silicon On Nothing.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a non-volatile memory cell and a fabrication method which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provide for a SONOS-type transistor memory cell having a minimum cross-sectional area of the active channel, at the same time allowing for an at least partial depletion of the channel region, and a method of producing such a memory cell and memory cell array.
It is a further object of the invention to disclose a method of fabricating NROM memory cells without using SOI substrates.
It is a yet a further object to provide an isolation of the memory cell that is self-aligned to the word line and suitable for an array of memory cells.
It is still a further object of the invention to provide an isolated channel transistor memory cell that can be arranged in a virtual-ground array, and a method of producing such a memory cell and memory cell array.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a non-volatile memory cell having a semiconductor structure (a semiconductor body or a semiconductor layer on a substrate); buried bit lines formed at the surface of the semiconductor structure and conductor strips on the surface applied to the bit lines; a source region and a drain region each connected by one of the bit lines; a gate dielectric formed on the surface at least between the source region and the drain region; a gate electrode disposed on the gate dielectric; and a word line electrically connected to the gate electrode, the word line crossing the bit lines and being electrically insulated from the bit lines.
The method comprises the following steps:
a) providing a semiconductor structure;
b) depositing a gate dielectric comprising a storage layer for trapping charge carriers;
c) depositing a layer for forming the gate electrode;
d) forming openings in the layer and forming spacers at sidewalls in the openings;
e) implanting a dopant through the openings to form the buried bit lines;
f) applying the conductor strips onto the buried bit lines, and applying electrically insulating cover layers onto the conductor strips;
g) applying at least one word line layer electrically connecting the gate electrode, and applying a hard mask layer on top of the at least one word line layer, the hard mask layer being used to structure the gate electrode and the at least one word line layer to form a word line stack;
h) etching on both sides of the word line stack between the bit lines anisotropically down into the semiconductor structure to a level below the source region and the drain region to form etch holes that are self-aligned to the word line stack; and
i) filling the etch holes with an electrically insulating material.
The NROM cell according to this invention is arranged at the surface of a semiconductor body or semiconductor layer supplied with electrically insulating regions extending vertically with respect to this surface straight down into the semiconductor body or semiconductor layer between bit lines and on both sides of a corresponding word line provided for addressing the memory cell, the electrically insulating regions being arranged self-aligned to the word line and possibly also self-aligned to the bit lines and extending at least to a lower boundary level of the source region and the drain region. The electrically insulating regions preferably comprise an undercut region or buried layer underneath the channel region that is situated between the regions of source and drain. Punching of the transistor is avoided or at least impeded by means of the electrically insulating regions.
The structure is produced by anisotropically etching between the word lines and bit lines after word line delineation at least to the level of the lower junctions of the source/drain regions and preferably by isotropically underetching the channel region of the transistor. This etching process takes place from both sides of the word line and is performed self-aligned to the word line. The etch holes and eventually the undercut are filled with an electrically insulating material. The gate reoxidation step can be used to grow a thermal oxide around the transistor body and to passivate the semiconductor surface. Additionally, boron dopant or another p-dopant species can be implanted for improved electrical insulation beneath the electrically insulating material filling the undercut.
A preferred embodiment comprises a deposition of a CVD oxide in combination with a dielectric material of a small value of the relative dielectric constant into the space between neighboring word lines.
The method is applicable to future memory devices appertaining to lithography generations with a word line half pitch of about 90 nm

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