Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-06-13
2004-05-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S397000, C438S301000, C438S643000, C438S945000, C438S253000, C438S254000, C257S303000, C257S301000, C257S306000, C257S316000, C257S530000
Reexamination Certificate
active
06734079
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic fabrications. More particularly, the present invention relates to microelectronic fabrications having microelectronic capacitor structures fabricated therein.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
In addition to the fabrication of transistor structures, resistor structures and diode structures within microelectronic fabrications, it is also common in the art of microelectronic fabrication to fabricate capacitor structures within microelectronic fabrications. Capacitor structures within microelectronic fabrications are employed within microelectronic fabrications including but not limited to: (1) data storage and retrieval microelectronic fabrications (such as semiconductor integrated circuit memory microelectronic fabrications); and (2) signal processing microelectronic fabrications (such as semiconductor integrated circuit mixed signal (i.e., mixed analog-digital VLSI devices and technology, microelectronic fabrications and semiconductor integrated circuit logic microelectronic fabrications).
While capacitor structures are thus clearly desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, capacitor structures are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, it is often difficult in the art of microelectronic fabrication to fabricate, with enhanced reliability and performance, microelectronic fabrications having formed therein capacitor structures.
It is thus desirable in the art of microelectronic fabrication to fabricate, with enhanced reliability and performance, microelectronic fabrications having formed therein capacitor structures.
It is towards the foregoing object that the present invention is directed.
Various capacitor structures having desirable properties, and methods for fabrication thereof, have been disclosed in the art of microelectronic fabrication.
Included among the capacitor structures and methods for fabrication thereof, but not limited among the capacitor structures and methods for fabrication thereof, are capacitor structures and methods for fabrication thereof disclosed within: (1) Liu et al., in “Single Mask Metal-Insulator-Metal (MIM) Capacitor With Copper Damascene Metallization for Sub-0.18 um Mixed Mode Signal and System-on-a-Chip (SoC) Applications, IEEE 2000 (0-7803-5327-2/00) (a planar capacitor structure formed with enhanced efficiency incident to being formed with a silicon nitride layer as both a diffusion barrier layer and a capacitor dielectric layer with respect to a capacitor plate layer formed of a copper containing conductor material); (2) Huang et al., in U.S. Pat. No. 6,146,941 (a capacitor structure formed with enhanced efficiency incident to being formed employing a pair of capacitor plate layers and a capacitor dielectric layer each formed into a self aligned contact region); (3) Adler et al., in U.S. Pat. No. 6,259,128 (a metal-insulator-metal (MIM) capacitor structure formed with enhanced performance incident to being formed employing multiple barrier layers); and (4) Tsu et al., in U.S. Pat. No. 6,294,420 (a capacitor structure having enhanced performance incident to being formed with a capacitor plate layer having formed thereupon a metal nitride layer in a self-aligned fashion).
The teachings of each of the foregoing references are incorporated herein fully by reference.
Desirable in the art of microelectronic fabrication are additional microelectronic fabrications with enhanced reliability and performance, as fabricated having formed therein capacitor structures.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a microelectronic fabrication having formed therein a capacitor structure and a method for fabricating the microelectronic fabrication having formed therein the capacitor structure.
A second object of the present invention is to provide the microelectronic fabrication and the method for fabricating the microelectronic fabrication in accord with the first object of the present invention, wherein the microelectronic fabrication is fabricated with enhanced reliability and performance.
In accord with the objects of the present invention, there is provided by the present invention a microelectronic fabrication and a method for fabricating the microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a capacitor comprising a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, where each of the foregoing layers has an exposed sidewall to thus form a series of exposed sidewalls. There is then formed passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.
The method for fabricating the microelectronic fabrication having formed therein the capacitor structure in accord with the present invention contemplates a microelectronic fabrication having formed therein the capacitor structure in accord with the present invention.
There is provided by the present invention a microelectronic fabrication having formed therein a capacitor structure and a method for fabricating the microelectronic fabrication having formed therein the capacitor structure, wherein the microelectronic fabrication is fabricated with enhanced reliability and performance.
The present invention realizes the foregoing object, in a first instance, by forming the capacitor structure within the microelectronic fabrication over a substrate, where the capacitor structure comprises a first capacitor plate layer having formed thereupon a capacitor dielectric layer in turn having formed thereupon a second capacitor plate layer, and where each of the foregoing layers has an exposed sidewall to thus form a series of exposed sidewalls. Similarly, the present invention also realizes the foregoing object, in a second instance, by forming passivating the series of exposed sidewalls of the first capacitor plate layer, the capacitor dielectric layer and the second capacitor plate layer a silicon oxide dielectric layer.
REFERENCES:
patent: 6069051 (2000-05-01), Nguyen et al.
patent: 6146941 (2000-11-01), Huang et al.
patent: 6259128 (2001-07-01), Adler et al.
patent: 6294420 (2001-09-01), Tsu et al.
patent: 6344964 (2002-02-01), Adler
patent: 6504203 (2003-01-01), Gambino et al.
patent: 6583491 (2003-06-01), Huang et al.
Liu, et al, “Single Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene Metallization for Sub-0.18&mgr;m Mixed Mode Signal and System-on-a-Chip (Soc) Applications”, IEEE 2000 (0-7803-6327-2/00).
Bao Tien-I
Chen Chun-Hon
Huang Chi-Feng
Jang Syun-Ming
Lin Chih-Hsien
Anya Igwe U.
Smith Matthew
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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