Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-07-09
2004-09-21
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
06795945
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for testing digital circuits having at least one circuit logic and memory elements, which are interconnected to form at least one shift chain, test vectors being inserted into the shift chain and result vectors being retrieved from the shift chain, and further relates to an arrangement for testing digital circuits having at least one circuit logic and memory elements which are interconnected to form at least one shift chain.
BACKGROUND INFORMATION
For the detection of faults in digital integrated circuits, test data may be fed to the circuits and the output data resulting from the test data and its processing within the digital circuits can be analyzed. For this purpose, memory elements, which may be components of the implementation to be tested, are interconnected to form long shift chains and the test data is inserted serially into these test chains as test vectors. Such methods may be referred to as “full scan” or “scan test.” These methods may be basically well suited to test digital integrated circuits, since, in principle, any scenarios with respect to the logic can be simulated and since, moreover, the memory elements, which are generally embodied as flip-flops, can be used efficiently in a dual function (as components of the digital circuit or as components of the shift chain). However, it must be noted that a considerable amount of time may be required for the test procedure due to the serial operation during insertion or during retrieval.
SUMMARY OF THE INVENTION
In an exemplary method, values from memory elements are fed back to logic units in at least one part of the shift chain, the feedback values are combined with updated output values of the circuit logic in the logic units, and in an internal test mode output values of the logic units are stored as internal test vectors in memory elements of the shift chain.
It is thus believed that the exemplary method of the present invention may provide an internal test mode in which the serial insertion and retrieval of test vectors may be eliminated. The provision of logic units and the combination of feedback values of the circuit logic with updated output values of the circuit logic taking place in them is believed to allow for producing a test vector having the character of a random value within the circuit.
Since the output values are stored in the memory elements in the internal test mode, upon completion of the internal test mode, it is believed that a significant value is available in the memory elements which provides information concerning the processes during the internal test mode. This significant value is also referred to as a signature, which may be useful in particular with respect to sporadically occurring circuit faults since even these are reflected in the signature. Therefore, it is believed that a fault can be largely isolated by retrieving and analyzing the signature.
The logic units may be assigned to memory elements of a shift chain, values from the memory elements being fed back to several logic units and the output values of the logic units being stored in the assigned memory elements. Thus, based on the unambiguous assignment between logic units and memory elements, it is established which information is contained in a particular memory element. Moreover, it is believed that the multiple feedback favors the generation of the random-like test vectors.
Subsequent to the internal test mode, a test vector may be inserted into a shift chain in a test scan mode and the output values of the logic units stored in the shift chain are retrieved. After an internal test mode, a conventional test scan mode may be switched over to either by inserting a calculated test vector or a random vector generated in an external module into the shift chain. Simultaneously, the retrieval of the shift chain subsequent to the internal test mode provides for detecting the signature which provides information concerning circuit faults occurring during the internal test mode.
Subsequent to a test scan mode, the test vector may be fed to the circuit logic and processed by the circuit logic and the output data of the circuit logic may be stored in memory elements of a shift chain. This corresponds to an operation in a conventional test method so that the invention can be advantageously combined with test methods of the related art.
Subsequent to a storage of output data of the circuit logic in memory elements of a shift chain in a test scan mode, a test vector may be inserted into a shift chain and the output data of the circuit logic stored in the memory elements of the shift chain may be retrieved. This is also an operation which is already used in methods of the related art. Now, however, both the output data of the circuit logic as a result of a conventional test scan mode and additionally the results of the internal test mode are available. A test of digital integrated circuits can thus be performed more efficiently and should yield more meaningful results.
Subsequent to a storage of output data of the circuit logic in memory elements of a shift chain in a test scan mode, the output data of the circuit logic stored in the memory elements of the shift chain may be retrieved. It is thus not necessary to insert a new test vector into the shift chain when the output data resulting from the test scan mode is retrieved. Termination of the test scan mode is prepared in this manner.
Accordingly, in an advantageous manner, it is possible that subsequent to a test scan mode, the digital circuit switches over to its normal operation. If no test vectors input from outside are present in the shift chain and if, moreover, the internal test mode is not activated, the memory elements can switch over to their normal function within the circuit and thus make a normal operation available.
The internal test mode may last for m clock pulses so that m internal test vectors are generated. The number m and accordingly the duration of the internal test mode may be selected to be more or less of any size. It is thus possible to optimize the number of clock pulses m with respect to the significance of the signature and the total duration of the test.
One phase of a test scan mode may last for n clock pulses so that a test vector with n components is inserted and retrieved. This corresponds to the known methods. The combination of the test scan mode for n clock pulses with the internal test mode for m clock pulses, however, considerably increases the relevance of the test results obtained in a specific time period.
The test vector may be fed to the circuit logic during a clock pulse. One clock pulse is sufficient to feed the test vector to the circuit logic in parallel after the insertion. Subsequent to this, it is immediately possible to shift to a different function which serves the purpose of optimizing the process time.
An exemplary embodiment and/or exemplary method involve the fact that at least one part of the shift chain is assigned to logic units, outputs of the memory elements of the shift chain are connected to inputs of logic units, and output values of a logic unit can be fed to inputs of memory elements. In addition to the coupling of the memory elements to an overall shift chain, local sub-chains can also be formed. The updated test results as well as the results of an internal test mode are available here in the form of a signature, from which it is possible to form new signature values by combining the updated test results with the previous memory values. Such a local feedback-signature forming logic makes it possible to determine particularly sound results from circuit elements connected upstream; in addition, the results of the local feedback-signature forming logic are used as test vectors for additional circuit components. Basically, it is within the context of the invention that the entire shift chain is equipped with local feedback-signature forming logics. However, it can be of particular advantage if the provision of local feedback-signature forming logics is li
De'cady Albert
Kenyon & Kenyon
Robert & Bosch GmbH
Trimmings John P
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