Non-volatile memory device and fabrication method thereof

Details Non-volatile memory device and fabrication method thereof Non-volatile memory device and fabrication method thereof

2002-04-25

2004-01-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S216000, C438S257000, C438S281000, C438S287000, C438S288000, C438S292000, C438S293000, C438S467000, C438S469000, C438S470000, C438S591000, C438S601000, C438S453000, C438S004000, C257SE21423, C257SE29300

Reexamination Certificate

active

06680227

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 91105279, filed on Mar. 20, 2002.
BACKGROUNDING OF THE INVENTION
1. Field of Invention
The present invention relates to a read-only memory device and the fabrication method thereof. More particularly, the present invention relates to a nonvolatile read only memory device and the fabrication method thereof
2. Description of Related Art
The current fabrication method for a non-volatile read only memory device comprises forming a trapping layer on a substrate, wherein the trapping layer is a stacked structure formed with a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. A read only memory device that uses an ONO composite layer as the trapping layer is known as a nitride read only memory (NROM). A polysilicon gate is then formed on the ONO layer, followed by forming a source region and a drain region on both sides of the ONO layer in the substrate.
The plasma used in the fabrication of a NROM causes a charge build-up on metal. This phenomenon is known as the “antenna effect”. When a transient charge imbalance occurs, charges are injected into the ONO layer inducing a programming effect, leading to the problem of a high threshold voltage. In general, the threshold voltage varies in a wild range of 0.3 V to 0.9 V.
Conventionally, the method to prevent the programming problem resulted from the antenna effect is to form a diode in the substrate connecting electrically with the word line. As the transient charges reach a specific value, the device is discharged by the electric breakdown of the diode. However, when the voltage induced by the charges is less than the breakdown voltage of the diode, the charges may still be injected into the ONO layer to induce the programming effect. In addition, such a design lowers the input voltage of the device and decreases the rate of the writing operation.
SUMMARY OF THE INVENTION
The present invention provides a non-volatile read only memory and the fabrication method thereof, wherein the plasma induced damages on a memory device are prevented.
The present invention provides a non-volatile read only memory and the fabrication method thereof, wherein the transient charge imbalance is obviated to prevent electric charges to be injected into the ONO layer, inducing the programming effect.
The present invention provides a non-volatile read only memory and the fabrication method thereof, wherein a high threshold voltage is prevented.
The present invention provides a non-volatile read only memory and the fabrication method thereof in which the programming problem due to the antenna effect, leading to a lower input voltage and a decrease in the rate of the writing operation is resolved
Accordingly, the present invention provides a non-volatile read only memory, wherein a word line is formed over a substrate, and the word line includes a metal layer and a polysilicon line. A trapping layer is located between the word line and the substrate. Moreover, the non-volatile read only memory further comprises a polysilicon protection line formed over the substrate. The polysilicon protection line electrically connects the word line and the grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.
The present invention provides another fabrication method for a non. volatile read only memory, wherein a non-volatile read only memory cell is formed on a substrate. A polysilicon protection line is further formed on the substrate. The polysilicon protection line and the word line of the non-volatile read only memory cell are connected, wherein the resistance of the polysilicon protection line is higher than that of the word line. Thereafter, a grounded doped region is formed in the substrate, followed by forming a contact on the substrate such that the contact connects the grounded doped region and the polysilicon protection line. A metal interconnect is then formed on the substrate. Subsequent to fab-out, a high voltage is applied to burn out the polysilicon protection line.
The present invention further provides another fabrication method for a non-volatile read only memory device, wherein a substrate comprising an isolation region is provided. A trapping layer is then formed on the substrate. After this, a polysilicon layer and a silicide layer are sequentially formed on the substrate. The above layers are further patterned to form a word line for the non-volatile read only memory and a polysilicon line. The thickness of a portion of the polysilicon line is reduced to form a polysilicon protection line above the isolation region. Thereafter, a dielectric layer is formed on the substrate to cover the above devices. A first contact and a second contact that connect the silicide layer and a doped region in the substrate are further formed in the dielectric layer. After the completion of the fabrication process, a high current is applied to burn out the polysilicon protection line.
The present invention provides a fabrication method for an electrically connected polysilicon protection line with the substrate to guide the charges built up in a fabrication process to the substrate. Damages induced to the ONO layer of the nonvolatile memory device and the programming effect are thus prevented. Subsequent to fab-out, a high current is used to burn out the polysilicon protection line, allowing the memory device to operate normally. The transient imbalance charges are discharged through the substrate to prevent the problems encountered in a high threshold voltage due to the trapping of charges in the ONO layer.
Since the resistance of the polysilicon protection line is higher than that of the word line, the polysilicon protection line is burnt out by using a high current after the manufacturing process is completed. Therefore, the input voltage is prevented from being lower to slow down the rate of the writing operation during a normal operation of the memory device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6147053 (2000-11-01), Nies
patent: 2001/0046718 (2001-11-01), Iranmanesh

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