Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-06
2004-04-06
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S393000, C438S238000, C438S266000
Reexamination Certificate
active
06716694
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and methods for manufacturing the same, and more particularly to semiconductor devices that mix-mount non-volatile semiconductor memory devices and semiconductor devices for an analog circuit, and methods for manufacturing the same.
BACKGROUND
In recent years, a mixed-mounting of various circuits is required in view of various demands such as a shortened chip-interface delay, a lowered cost per circuit board, a lowered cost in design and development of a circuit board and the like. A mixed-mounting technology for mounting memories and analog ICs has become one of the important technologies.
SUMMARY
Certain embodiments relate to a method for manufacturing a semiconductor device including a memory region including a non-volatile memory transistor with a split gate structure, and a capacitor region including a capacitor. The method includes forming, in the memory region, a gate insulation layer, a floating gate, and a selective oxide insulation layer on a semiconductor substrate, which comprise a portion of the non-volatile memory transistor. In the capacitor region, a lower electrode that comprises a portion of the capacitor on an insulation layer is formed on the semiconductor substrate. The method also includes successively depositing in layers a first silicon oxide layer and a protection layer for the memory region, and then removing, in the capacitor region, the first silicon oxide layer and the protection layer deposited over the lower electrode. In the capacitor region, an insulation layer is formed by thermally oxidizing an upper surface section of the lower electrode. The method also includes depositing a silicon nitride layer, and then removing the protection layer and the silicon nitride layer in the memory region, and patterning the silicon nitride layer in the capacitor region. The method also includes forming an intermediate insulation layer and a control gate that comprise a portion of the non-volatile memory transistor, and forming a dielectric layer and an upper electrode that comprise a portion of the capacitor, wherein the control gate and upper electrode are formed by forming and then patterning a conduction layer, wherein the intermediate insulation layer is formed by patterning the first silicon oxide layer; and wherein the dielectric layer is formed between the upper electrode and the lower electrode. In addition, an impurity diffusion layer is formed by introducing an impurity in a specified region in the semiconductor substrate.
In one aspect of certain embodiments such as that described above, the control gate that forms a portion of the non-volatile memory transistor and the upper electrode that forms a portion of the capacitor are formed in a common patterning step. In another aspect of certain embodiments, the floating gate that forms a portion of the non-volatile memory transistor and the lower electrode that forms a portion of the capacitor are formed in a common patterning step.
Embodiments also include a method for manufacturing a semiconductor device that mix mounts non-volatile memories and analog integrated circuits. The method includes forming, in a memory region, a gate insulation layer, a floating gate, and a selective oxide insulation layer on a semiconductor substrate. The method also includes forming, in a capacitor region, an insulation layer and a lower electrode. In addition, in the capacitor region, an insulation layer is formed by thermally oxidizing an upper surface section of the lower electrode. In addition, in the memory region, an intermediate insulation layer and a control gate are formed. In addition, in the capacitor region, a dielectric layer and an upper electrode are formed. The floating gate and the lower electrode are formed in a common processing step. In an aspect of certain embodiments, the control gate and the upper electrode are formed in a common processing step.
Embodiments also include a method for manufacturing a semiconductor device that mix mounts non-volatile memories and analog integrated circuits, including forming, in a memory region, a gate insulation layer, a floating gate, and a selective oxide insulation layer on a semiconductor substrate. The method also includes forming, in a capacitor region, an insulation layer and a lower electrode on the semiconductor substrate. In addition, the method includes forming a first silicon oxide layer and a protection layer on the selective oxide insulation layer in the memory region. The method also includes forming, in the capacitor region, an insulation layer by thermally oxidizing an upper surface section of the lower electrode. In addition, in the memory region, an intermediate insulation layer and a control gate are formed, and in the capacitor region, a dielectric layer and an upper electrode are formed. In on aspect of certain embodiments, the protection layer comprises silicon nitride.
Embodiments also include a semiconductor device including non-volatile memories and analog integrated circuits formed on a substrate. The device includes a memory region including a gate insulation layer, a floating gate, and a selective oxide insulation layer on a semiconductor substrate. The device also includes a capacitor region including an insulation layer and a lower electrode on the semiconductor substrate. The memory region also includes a first silicon oxide layer and a protection layer on the selective oxide insulation layer. The capacitor region also includes a thermally oxidized insulation layer on an upper surface section of the lower electrode. The device also includes an intermediate insulation layer and a control gate in the memory region, and a dielectric layer and an upper electrode in the capacitor region. In one aspect of certain embodiments, the protection layer comprises silicon nitride.
REFERENCES:
patent: 6339000 (2002-01-01), Bhattacharya et al.
patent: 6395590 (2002-05-01), Leu
patent: 2000-216274 (2000-08-01), None
Gary E. McGuire, “Semiconductor Materials and Process Technology Handbook,” Noyes Publ., Norwich, New York, (1988) p. 303.*
Arthur Sherman, “Chemical Vapor Deposition for Microelectronics,” Noyes Publ., Westwood, New Jersey, (1987), p. 68.*
S. Wolf, “Silicon Processing fror the VLSI Era: vol. 2—Process Integration,” Lattice Press, Sunset Beach, CA (1990), pp. 20-22.
Konrad Raynes & Victor LLP
Lee Eddie
Magee Thomas
Raynes Alan S.
Seiko Epson Corporation
LandOfFree
Semiconductor devices and methods for manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor devices and methods for manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor devices and methods for manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3246447