Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-07-19
2004-07-06
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S360000, C257S372000
Reexamination Certificate
active
06759716
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an input/output protection device for a semiconductor integrated circuit.
DESCRIPTION OF THE PRIOR ART
In general, since complementary metal oxide semiconductor (CMOS) transistors included in a semiconductor integrated circuit become quite smaller in size, it is increasingly difficult for an input/output protection device for such a semiconductor integrated circuit to protect the device against electrostatic discharge (ESD). That is, when the CMOS transistor including a gate oxide film is reduced in size, the film becomes thinner and hence its dielectric tolerance is decreased. Recently, to reduce parasitic resistance of such a transistor including a diffusion layer, a metal silicidation of the diffusion layer has been applied. This also causes lowering ESD tolerance.
Heretofore, a parasitic lateral type bipolar transistor has been employed as a semiconductor integrated circuit including a CMOS of the prior art. Various techniques of this kind have been proposed in various articles, for example, in the Japanese Patent Laid-Open Nos. 8-51188 and 7-122715.
Referring now to
FIGS. 5A and 5B
, description will be given of a representative example of an input/output protection device including a bipolar transistor of parasitic lateral type of the prior art.
FIG. 5A
shows in a plan view the input/output protection device.
FIG. 5B
is a cross-sectional view thereof along a direction X-Y of FIG.
5
A. As can be seen from
FIG. 5B
, this configuration includes a p-type well layer
102
on a surface of a p-type silicon substrate
101
. On a surface of p-type well layer
102
, a device isolation film
103
is selectively fabricated.
Moreover, an n-type first diffusion layer
104
is formed on a surface of p-type well layer
102
and an n-type second diffusion layer
105
is manufactured on another surface of p-type well layer
102
. The configuration further includes a p-type lead diffusion layer
106
. First and second diffusion layers
104
and
105
are manufactured in a process in which a diffusion layer is formed as a source-drain region of a CMOS transistor.
In this structure, first diffusion layer
104
is connected to an input/output terminal
107
. Second diffusion layer
105
and diffusion layer
106
are linked with a ground terminal
108
.
In the input/output protection device configured as above, when a positive, high-voltage pulse is applied to input/output terminal
107
, an avalanche breakdown takes place in a region of junction between first diffusion layer
104
and p-type well layer
102
. This causes a breakdown current to flow from input/output terminal
107
to diffusion layer
106
. The breakdown current locally increases potential in p-type well layer
102
to operate a bipolar transistor of lateral type including first diffusion layer
104
as a collector, second diffusion layer
105
as an emitter, and p-type well layer
102
as a base. As a result of operation of this transistor, i.e., a parasitic bipolar transistor, ESD current flows from input/output terminal
107
via second diffusion layer
105
as the emitter to ground terminal
108
.
Since the degree of integration of semiconductor integrated circuits is increased and its operation speed becomes higher, semiconductor elements of these circuits are decreased in size and the density thereof becomes greater. In general, this resultantly increases the number of defects in the semiconductor elements due to electrostatic discharge (ESD).
The bipolar transistor of parasitic lateral type cannot appropriately respond to a positive high-voltage pulse with a high-speed or a steep rising edge. Consequently, before the protection device starts its functions, a gate oxide film in its internal circuit is possibly destroyed in many cases. As the size of semiconductor integrated circuits is decreased, the gate oxide film becomes thinner and therefore is more easily destroyed.
In the bipolar input/output protection device of lateral type above, the breakdown current after the avalanche breakdown flows through a region of p-type well layer
102
having lower resistance than p-type silicon substrate
101
. Therefore, potential of p-type well layer
102
as the base of the bipolar transistor cannot be quickly increased. This leads to a problem of a slow response of the input/output protection device. The goal of the present invention provides to a lateral bipolar type input/output protection device which rapidly responds to an over voltage pulse and/or over current.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an input/output protection device of a lateral bipolar type having a high response to an excess voltage pulse and/or an excess current pulse associated with, for example, ESD phenomena.
In accordance with the present invention, there is provided an input/output protection device for a semiconductor integrated circuit including a substrate of a first conduction type, an internal circuit, an input/output terminal, electrode wiring, and signal wiring. The device includes a first diffusion layer fabricated in a region of the first conduction type of the semiconductor substrate, the layer having a second conduction type opposite to the first conduction type and being connected to the input/output terminal; a second diffusion layer of the second conduction type connected to the electrode wiring kept, the electrode wiring being at a predetermined potential; and a third diffusion layer of the second conduction type fabricated at a bottom of the second diffusion layer, the third diffusion layer being connected to the second diffusion layer. The first diffusion layer is circularly enclosed with the second and third diffusion layers.
In the configuration, the region of the first conduction type of the semiconductor substrate includes a fourth diffusion layer having an impurity concentration higher than that of the semiconductor substrate. The impurity concentration of the fourth diffusion layer monotonously decreases in a direction from a surface of the semiconductor substrate to an inner section thereof. The third diffusion layer has a depth equal to or more than that of the fourth diffusion layer.
When a high voltage is applied to the input/output terminal, there is formed and is operated a lateral, bipolar transistor including the first diffusion layer as a collector, the second and third diffusion layers as an emitter, and the region of the first conduction type or the fourth diffusion layer as a base.
In the input/output protection device for a semiconductor integrated circuit in accordance with the present invention, the first and second diffusion layers are isolated from each other by a device separating isolation layer on a surface of the semiconductor substrate. Alternatively, the first and second diffusion layers are fabricated with a gate electrode disposed on a surface of the semiconductor substrate. In the structure, the device separating isolation layer or the gate electrode is fabricated in a circular contour.
Additionally, the gate electrode is connected to the signal wiring of the internal circuit of the semiconductor integrated circuit. The gate electrode is fixed to a predetermined potential.
In the input/output protection device for a semiconductor integrated circuit above, the first conduction type is a p type and the second conduction type is an n type, or the first conduction type is an n type and the second conduction type is a p type. The predetermined potential is a potential of a power source.
As above, In the input/output protection device for a semiconductor integrated circuit in accordance with the present invention, the first diffusion layer as the collector region of the parasitic, lateral bipolar transistor is circularly enclosed with the third diffusion layer. Consequently, the breakdown current appearing at occurrence of an avalanche breakdown in a junction region between the first diffusion and the region of the first conduction type flows laterally in the third diffusion layer. This curren
Fahmy Wael
McGinn & Gibb PLLC
NEC Electronics Corporation
Nguyen Dilinh
LandOfFree
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