Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-12-05
2004-05-18
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S639000, C438S687000, C438S695000, C438S696000, C438S723000, C438S725000, C438S736000
Reexamination Certificate
active
06737349
ABSTRACT:
BACKGROUND
1. Technical Field
Methods of forming copper wirings in semiconductor devices are disclosed. More particularly, methods of forming copper wirings in semiconductor devices are disclosed, which can prevent an increase of a dielectric constant of a low dielectric constant film and poor deposition of a copper anti-diffusion film due to infiltration of an organic solvent, etch gas, etc. into the low dielectric constant film exposed at the side of a damascene pattern during a wet cleaning process for removing polymer generated when a portion of the low dielectric constant film is etched to form the damascene pattern or during a photoresist pattern strip process.
2. Description of the Related Art
Generally, as the semiconductor industry shifts to an ultra large-scale integration (ULSI) level, the geometry of the semiconductor device is narrowed to a sub-half-micron but the circuit density is increased in view of performance improvement and reliability. In order to meet these needs, a thin copper film has been used as an interconnection material useful for the integration circuit in forming a metal wiring in the semiconductor device, since copper has a higher melting point and higher resistance against the electro-migration (EM) than aluminum and can thus improve reliability of the devices.
Methods of burying copper that are currently available are a physical vapor deposition (PVD) method, a reflow method, a chemical vapor deposition (CVD) method, an electroplating method, an electroless-plating method, and the like. Among them, the electroplating method and the CVD method that have a relatively good copper burial characteristic are preferred.
Further, a damascene scheme, by which a via contact hole electrically connected to a lower layer and a trench in which a metal wiring is located are simultaneously formed, has been widely employed in a process of forming the copper wiring in the semiconductor device. At this time, a low dielectric constant film is used.
Today, in the damascene method of forming the copper wiring, the low dielectric constant film having a dielectric constant of below 2.5 in the semiconductor device has been basically used. An ultra low dielectric constant film has lots of apertures within the film. In the wet cleaning process for removing polymer generated due to the etch process of forming the damascene pattern or a process for removing a photoresist pattern, an organic solvent, an etch gas, etc. is infiltrated into the porous ultra low dielectric constant film exposed at the side of the damascene pattern. As a result, the apertures in the ultra low dielectric constant film are filled with the organic solvent having a high dielectric constant. The dielectric constant of the entire wiring structure is thus increased. Further, in a subsequent process of depositing a copper anti-diffusion film, the organic solvent evaporates from the ultra low dielectric constant film at the side of the damascene pattern. Therefore, the fineness and close adhesion properties of the copper anti-diffusion film are degraded.
SUMMARY OF THE DISCLOSURE
Methods of forming copper wirings in semiconductor devices are disclosed which are capable of improving the electrical characteristic and reliability of the copper wiring by preventing infiltration of organic solvent, etch gas, etc. into a porous low dielectric constant film.
A disclosed method of forming a copper wiring in a semiconductor device comprises providing a semiconductor substrate on which a lower metal wiring is formed, forming a low dielectric constant film on the entire structure including the lower metal wiring, forming a hard mask layer on the low dielectric constant film, forming a photoresist pattern on the hard mask layer and then etching a portion of the low dielectric constant film by means of an etch process using the photoresist pattern and hard mask layer as masks, thus forming a damascene pattern, whereby a polymer having the formula CF
X
H
Y
is generated in the etch process of forming the damascene pattern and the polymer sticks to the side of the damascene pattern to form a polymer layer, changing the polymer layer to a SiCH film using SiH
4
plasma and then removing the photoresist pattern, and forming a copper layer on the entire structure including the low dielectric constant film surrounded by the hard mask layer and the SiCH film and then polishing the copper layer by means of a chemical mechanical polishing process to form a copper wiring.
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patent: 6465159 (2002-10-01), Ni et al.
patent: 6475904 (2002-11-01), Okoroanyanwu et al.
patent: 6528884 (2003-03-01), Lopatin et al.
patent: 2002/0173142 (2002-11-01), Vanhaelemeersch et al.
patent: 2003229482 (2003-08-01), None
Gurley Lynne
Hynix / Semiconductor Inc.
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