Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

2003-07-09

2004-09-07

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S267000

Reexamination Certificate

active

06787417

ABSTRACT:

Japanese Patent Application No. 2002-204274, filed on Jul. 12, 2002, is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device that comprises a memory region and a logic circuit, and, more particularly, to a method of fabricating a semiconductor device wherein a non-volatile storage device formed in the memory region has two charge accumulation regions for one word gate.
One type of non-volatile semiconductor storage device is called a metal-oxide-nitride-oxide semiconductor (MONOS) type or silicon-oxide-nitride-oxide-silicon (SONOS) type, wherein a gate dielectric layer between a channel region and a control gate is formed of a multi-layer stack of silicon oxide and silicon nitride layers, and charge is trapped in the silicon nitride layer.
A device shown in
FIG. 18
is known as an example of this MONOS type of non-volatile semiconductor storage device (disclosed by Y. Hayashi, et al, in 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123).
In this MONOS memory cell
100
, a word gate
14
is formed over a semiconductor substrate
10
with a first gate dielectric layer
12
interposed in between. A first control gate
20
and a second control gate
30
are formed on either side of the word gate
14
, in the shape of side walls. There is a second gate dielectric layer
22
between a base portion of the first control gate
20
and the semiconductor substrate
10
, and a dielectric layer
24
between a side surface of the first control gate
20
and the word gate
14
. In a similar manner, the second gate dielectric layer
22
is between a base portion of the second control gate
30
and the semiconductor substrate
10
, and the
24
is between a side surface of the second control gate
30
and the word gate
14
. Impurity layers
16
and
18
, which are to form a source region and drain region, are formed in the semiconductor substrate
10
between the opposing control gates
20
and
30
of neighboring memory cells.
In this manner, each memory cell
100
has two MONOS memory elements on the side surfaces of the word gate
14
. These two MONOS memory elements can be controlled independently, and thus one memory cell
100
can store two bits of information.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a method of fabricating a semiconductor device that comprises a MONOS type of non-volatile storage device having two charge accumulation regions, wherein a memory region comprising a MONOS type of memory cell and a logic circuit region comprising a peripheral circuit for the memory are formed on the same substrate.
According to the present invention, there is provided a method of fabricating a semiconductor device that comprises a memory region including a non-volatile storage device and a logic circuit region including a peripheral circuit for the non-volatile storage device, the method comprising steps of:
(a) forming a first dielectric layer over a semiconductor layer,
(b) forming a first conductive layer over the first dielectric layer,
(c) forming a stopper layer over the first conductive layer,
(d) patterning the stopper layer and the first conductive layer within the memory region,
(e) forming a charge accumulation film over the memory region and the logic circuit region,
(f) forming a second conductive layer over the charge accumulation film, then forming control gates in the form of side walls over both side surfaces of the first conductive layer within at least the memory region with the charge accumulation film interposed in between, by anisotropic etching of the second conductive layer,
(g) forming first side wall dielectric layers on at least upper portions of the control gates and over both side surfaces of a laminate formed of the stopper layer and the first conductive layer,
(h) removing the stopper layer from within the logic circuit region,
(i) patterning the first conductive layer within the logic circuit region, to form a gate electrode of an insulated-gate field-effect transistor within the logic circuit region,
(j) forming side wall dielectric layers on both side surfaces of the gate electrode, and also forming a second side wall dielectric layer so as to cover each of the first side wall dielectric layers and each of the control gates,
(k) forming first impurity layers, each of which becomes a source region or a drain region of the non-volatile storage device and forming second impurity layers, each of which becomes a source region or a drain region of the insulated-gate field-effect transistor,
(l) forming silicide layers on the surfaces of the first impurity layers and the second impurity layers,
(m) forming a second dielectric layer over the memory region and the logic circuit region,
(n) removing the second dielectric layer in such a manner that the stopper layer is exposed within the memory region and also the gate electrode is not exposed within the logic circuit region,
(o) removing the stopper layer from within the memory region, and
(p) patterning the first conductive layer within the memory region, to form a word gate for the non-volatile storage device within the memory region.


REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6133098 (2000-10-01), Ogura et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6395596 (2002-05-01), Chien et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 6531350 (2003-03-01), Satoh et al.
patent: A 7-161851 (1995-06-01), None
patent: B1 2978477 (1999-09-01), None
patent: A 2001-156188 (2001-06-01), None
U.S. patent application Ser. No. 10/636,582, Inoue, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/636,562, Inoue, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/689,990, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/636,581, Yamamukai, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/690,025, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/689,993, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/689,987, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/244,627, Ebina et al., filed Sep. 17, 2002.
U.S. patent application Ser. No. 10/234,197, Ebina et al., filed Sep. 5, 2002.
U.S. patent application Ser. No. 10/339,555, Shibata, filed Jan. 10, 2003.
U.S. patent application Ser. No. 10/350,010, Kasuya, filed Jan. 24, 2003.
U.S. patent application Ser. No. 10/349,943, Kasuya, filed Jan. 24, 2003.
U.S. patent application Ser. No. 10/234,095, Ebina et al., filed Sep. 5, 2002.
U.S. patent application Ser. No. 10/052,255, Ebina et al., filed Jan. 23, 2003.
U.S. patent application Ser. No. 10/052,549, Ebina et al., filed Jan. 23, 2002.
U.S. patent application Ser. No. 10/244,623, Ebina et al., filed Sep. 17, 2002.
U.S. patent application Ser. No. 10/350,075, Kasuya, filed Jan. 24, 2003.
U.S. patent application Ser. No. 10/342,307, Ueda, filed Jan. 15, 2003.
U.S. patent application Ser. No. 10/349,958, Kasuya, filed Jan. 24, 2003.
U.S. patent application Ser. No. 10/339,558, Inoue, filed Jan. 10, 2003.
Hayashi et al., “Twin MONOS Cell with Dual Control Gates,” IEEE Symposium on VLSI Technology Digest of Technical Papers, 2000.
Chang et al., “A New SONOS Memory Using Source-Side Injection for Programming,” IEEE Electron Device Letters, vol. 19, No. 7, pp. 253-255, Jul. 1998.
Chen et al., “A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN),” Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64, 1997.

Affiliated with

Also associated with

Rating

Method of fabricating semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3234170