Method of forming capacitor of a semiconductor memory device

Details Method of forming capacitor of a semiconductor memory device Method of forming capacitor of a semiconductor memory device

2002-06-12

2004-01-06

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S381000

Reexamination Certificate

active

06673668

ABSTRACT:

This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2001-32686 fled in Korea on Jun. 12, 2001, which is herein incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of the semiconductor memory device.
DESCRIPTION OF THE PRIOR ART
A Dynamic Random Access Memory (DRAM) cell is a semiconductor memory device typically having one transistor and one capacitor, in which one bit of data is stored in a cell using an electric charge.
A capacitor has a lower electrode, a dielectric layer, and an upper electrode. One electrode of the lower electrode and the upper electrode is connected to the source/drain junction of the transistor, and the other electrode is connected to a reference voltage line.
As the integration of the DRAM is increased, the size of the memory cell is decreased. However, it is impossible to reduce the size of the memory cell in proportion to the reduction of the DRAM size, because an adequate amount of the capacitance is needed to prevent soft error and to maintain stable operation. There have been efforts to obtain adequate capacitance by reducing the thickness of the dielectric layer, increasing the effective area and using material having a high dielectric constant.
The dielectric layer of a conventional capacitor is formed with a SiO
2
layer, a nitride-oxide (NO) layer or an oxide-nitride-oxide (ONO) layer. The NO layer and the ONO layer are formed with a Si
3
N
4
layer of which the dielectric constant is two times as high as that of the SiO
2
layer.
However, it is impossible to obtain high capacitance from the SiO
2
layer, Si
3
N
4
layer, NO layer and ONO layer because of the low dielectric constant of the dielectric layers, even when the thicknesses of the dielectric layers are reduced and the areas are increased. Therefore, dielectric layers, such as (Ba, Sr) TiO
3
(hereinafter referred as BST) layer, (Pb, Zr) TiO
3
(hereinafter referred as PZT) layer and Ta
2
O
5
layer, having high dielectric constant are used as a dielectric layer of the capacitor.
The dielectric constant of the Ta
2
O
5
is about 20 to 25, which is three times as high as that of the Si
3
N
4
, and it is relatively easier to etch the Ta
2
O
5
layer than to etch the BST layer and PZT layer. Furthermore, the Ta
2
O
5
layer formed by the chemical vapor deposition (CVD) method has a good characteristic of step coverage. However, it is difficult to compose the Ta
2
O
5
layer with the proper stoichiometry. Therefore, recently, a TaON layer has been suggested to overcome the stoichiometry problem of the Ta
2
O
5
layer.
The characteristic of the Ta
2
O
5
layer depends on the electrodes of the capacitor. A capacitor having a Ta
2
O
5
layer as a dielectric layer has a MIS structure. Herein, “M” is a metal layer for forming the plate line; “I” is an insulating layer i.e., the dielectric layer of the capacitor; and “S” is a polysilicon layer for forming a storage electrode. The plate line of the capacitor having the Ta
2
O
5
layer may also be formed with stacked layers of polysilicon layer/TiN layer or polysilicon layer/WN layer, and the storage electrode may also be formed with a polysilicon layer of which surface is treated with nitrogen by the rapid thermal nitration (RTN) process.
In a Metal/Insulator/Silicon (MIS) structure, the thickness of Ta
2
O
5
can be reduced to secure proper capacitance needed in the highly integrated circuit device. The thermal treatment performed after the formation of the capacitor is important in reducing the thickness of the Ta
2
O
5
layer. That is, if the thermal burdens of subsequent processes are relative low, then it is possible to make the Ta
2
O
5
layer relatively thinner. The minimum thickness of the Ta
2
O
5
layer has not clearly been proved, but the limit is presumed to be about 20-30 Å. If the thickness of the Ta
2
O
5
layer is decreased more than the limit, the problem of increasing leakage current occurs.
To reduce the thickness of the dielectric layer, the lower electrode may be formed with a metal layer instead of a polysilicon layer. When forming the lower electrode with a metal, the native oxide, which becomes a disturbance to reduce the thickness of dielectric layer, is not formed on the surface of the lower electrode. Accordingly, it is possible to reduce the thickness of Ta
2
O
5
layer by forming the lower electrode with metal instead of polysilicon.
However, the characteristic of the leakage current is influenced greatly by the quality of the lower electrode when the lower electrode is made with metal. Accordingly, a barrier layer should be formed under the lower electrode to prevent the reaction between the metal layer and a polysilicon plug (or a silicon substrate) and to prevent the diffusion of the oxygen used as a source for forming a dielectric layer.
In the meantime, the dielectric characteristic of the tantalum-contained-oxide layer, such as Ta
2
O
5
and TiON, depends on the material of the upper electrode.
A Titanium-Nitride (TiN) layer is relatively stable among the conductive materials, and the TiN layer has good step coverage because the TiN layer can be formed by the chemical vapor deposition method. Therefore, a TiN layer is widely used to form the upper electrode. When forming the upper electrode with TiN, a good electric characteristic of the capacitor can be obtained when the TiN layer is formed at a relatively low temperature rather than a relatively high temperature. However, if the TiN layer is formed at a low temperature, the tantalum-contained-dielectric layer, such as Ta
2
O
5
and TiON, is damaged by Cl radicals generated by the source material TiCl
4
. In addition, the structure of the TiN layer formed at a low temperature is not dense, whereby deoxidized Ta elements remain at the interface between the tantalum-contained-oxide layer and the TiN layer, and the leakage current caused by the Ta elements deteriorates the electric characteristic of the capacitor.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method of fabricating a capacitor having a tantalum-contained-dielectric layer.
It is, therefore, another object of the present invention to provide a method of fabricating a capacitor capable of obtaining good electric characteristics and reducing damages from Cl radicals.
According to one embodiment of the present invention, there is provided a method of forming a capacitor of a semiconductor device, including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing Ta element on the lower electrode; forming a first TiN layer of an upper electrode on the dielectric layer by using atomic layer deposition; forming an oxidized TiN layer by performing an oxidation process on the dielectric layer; and forming a second TiN layer of the upper electrode on the oxidized TiN layer by using a physical vapor deposition (PVD).
According to a second embodiment of the present invention, there is provided a capacitor of a semiconductor device including: a lower electrode formed over a semiconductor substrate; a dielectric layer containing a Ta element formed on the lower electrode; and an upper electrode formed on the dielectric layer. The upper electrode has an oxidized layer and a titanium containing layer. The oxidized layer is between the TiN layer and the dielectric layer. Additionally, the dielectric layer has an absorption region where the dielectric layer has absorbed a precursor such as TiCl
4
during atomic vapor deposition (AVD).
These and other objects of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invent

Affiliated with

Also associated with

Rating

Method of forming capacitor of a semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of forming capacitor of a semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming capacitor of a semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3232538