Method for calculation of cell delay time

Details Method for calculation of cell delay time Method for calculation of cell delay time

2000-11-17

2004-04-06

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S121000

Reexamination Certificate

active

06718529

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a delay calculation method and to a layout optimization method for high-accuracy delay time calculation of cells and wires in timing verification during the design of a semiconductor integrated circuit. Today, because of advances in semiconductor process technology, the size of transistors have been miniaturized and reduced down to less than 0.5 &mgr;m (submicron size). Also with respect to rooting of wires, both the wire pitch and the wire width tend toward being shrunk. Therefore, when calculating a length of time taken for a signal to propagate in a large-scale integrated circuit (hereinafter called the “delay time”), it now becomes necessary to pay attention to the influence of the resistance of a wire and the influence of an adjacent wire. These influences have not been taken into much consideration so far.
For the development of high-integration, high-function, high-performance semiconductor LSI circuits, several techniques have been proposed or already put into practice for high-accuracy calculation of the delay time of a wire between cells forming the aforesaid delay time and the delay time of the cells.
Hereinafter, a conventional, post-layout design flow and a cell delay time/wire delay time calculation process procedure will be explained by making reference to FIG.
13
. Note that throughut the specification the term “cell” is so defined as to include not only a logical unit such as an inverter and a buffer but also a functional macroblock. Further, the term “instance” is the name for the purpose of identifying cells as different cells even when they have the same logic. This will be explainedtusing a concrete example (FIG.
14
). Both an instance
1400
and an instance
1401
are buffer cells. However, in order to deal with these instances as different components, they are named the instance
1400
and the instance
1401
.
A conventional design flow and its associated delay calculation method will be described (FIG.
13
).
In the layout step S
1300
of the design flow (FIG.
13
), a delay library
1300
is used to generate a layout
1301
corresponding to a net list
1101
. In the layout step S
1300
, a delay calculation tool mounted in the layout tool is used for timing driven layout in which placement/wire routing is carried out while performing instance and wire delay time. calculations. In the timing driven layout, a layout step is carriel out according to the timing calculated by the delay calculation tool, which is a possible reason for reduction in returning back to a particular design step due to timing errors of a subsequent design flow. However, when performing a timing driven layout in the layout step S
1300
, if a delay calculation algorithm different from one used in the delay calculation step S
1302
is employed, this causes these two steps to produce different delay calculation results. For this reason, the problem with a layout by the timing driven layout is that the design flow is returned back to a particular design step due to the fact that different delay calculation algorithms produce different delay calculation results.
However, even when both the delay calculation tool and the layout tool employ the same delay calculation algorithm, if the layout step S
1300
generates a layout shape that does not allow the delay calculation algorithm to perform delay calculations at high accuracy, this results in poor delay calculation accuracy.
Here, by “the layout shape” is meant the shape of a cell, the drive power of a cell, or the like in a layout. In the timing driven layout, a layout step is carried out while the cell delay time, input slew rate, load capacitance, and wire delay time are calculated from the shape.
Therefore, the layout step S
1300
is required to generate a layout having such a layout shape capable of allowing high-accuracy delay calculations in the delay calculation step S
1302
for timing error reduction and reduction in returning back to a particular design step due to poor delay calculation accuracy. However, such a measure has not yet been taken so far.
Next, in the RC extraction step S
1301
, the layout
1301
is input and wire parasitic resistance and capacitance are extracted to generate RC information
1102
. This RC information
1102
can be expressed in various formats such as DSPF (Standard Parasitic Format: Cadence Design Systems, “Cadence Standard Parasitic Format”, August 1993).
This is followed by the delay calculation step S
1302
in which the RC information
1102
and the delay library
1300
are input and the delay times of an instance and a wire in the layout
1301
are calculated and delay information
1302
is output.
Further, in the timing simulation step S
1303
, while the net list
1101
is collated with the delay information
1302
, a timing simulation is carried out to provide a simulation result
1303
. The LSI designer looks at the simulation result
1303
and if an timing error is output, then the LSI designer returns back to a necessary design step to redo the design.
As the delay calculation method available in the delay calculation step S
1302
, there are several types of delay time calculation methods. These delay calculation methods will be explained below.
Whereas one of the delay calculation methods (
FIG. 14
) does not closely deal with the propagation of a signal waveform, the other delay calculation method (
FIG. 16
) closely deals with the propagation of a signal waveform.
Each of these delay calculation methods will be described. FIG.
14
(
a
) is a conceptual diagram showing a concept relating to the propagation of a waveform for the first delay calculation method. FIG.
14
(
b
) is a diagram showing a procedure of the first delay calculation method. FIG.
14
(
c
) is a diagram showing the division of the first delay calculation method.
The first delay calculation method of FIG.
14
(
a
) is characterized in that the signal waveform propagation between an input and output of a wire
1402
driven by the instance
1400
is calculated and the signal waveform propagation between the input and output terminals of each instance
1400
and
1401
is not taken into consideration.
As more concretely shown in FIG.
14
(
b
), in the instance output signal waveform calculation step, giving attention to the fact that the instance
1400
drives the wire
1402
and the instance
1401
, a circuit equation at the output terminal of the instance
1400
is set up. Then, the circuit equation is solved thereby to calculate a signal waveform (or an input signal waveform of the wire
1402
)
1404
at the output terminal of the instance
1400
.
Next, in the wire output signal waveform calculation step, if the signal waveform
1404
is fed to the wire
1402
, then a circuit equation at the output of the wire
1402
is set up. Then, the circuit equation is solved thereby to calculate a signal waveform
1405
at the output of the wire
1402
, i.e., an input signal waveform of the instance
1401
.
These two steps described above are repeatedly performed on every instance and wire thereby to calculate signal waveforms at the input and output terminals of all the instances for instance delay time calculation and wire delay time calculation.
The algorithm of the first delay calculation method is characterized in that a wire and an instance that is connected to the wire are single split units
1407
and
1408
(see FIG.
14
(
c
)). These split units
1407
and
1408
are independent from each other. Accordingly, there is no need to propagate signals in order in the signal propagation direction, therefore producing the advantage of requiring a less length of delay calculation processing time.
However, the first delay calculation method has some problems (FIG.
15
). The problems of the first delay calculation method will be described below in detail.
Suppose here that the wire
1402
is several times greater than a wire
1410
in resistance and capacitance. In the already-described first delay calculation method, calculations are performed wherein the split units

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