Methods for manufacturing semiconductor devices and...

Details Methods for manufacturing semiconductor devices and... Methods for manufacturing semiconductor devices and...

2001-09-26

2004-07-13

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S303000, C438S305000, C438S591000, C438S785000

Reexamination Certificate

active

06762102

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices having a field effect transistor and methods for manufacturing the same, and more particularly, to semiconductor devices having a gate electrode that is formed from two or more layers and methods for manufacturing the same.
RELATED ART
Currently, there is a technique in which a gate electrode
230
of a MOS transistor
300
shown in FIG.
10
(
b
) is formed by a so-called damascene method. One example of a method for manufacturing a MOS transistor
300
using a technique in which its gate electrode
230
is formed by a damascene method is described below.
As shown in FIG.
9
(
a
), a gate dielectric layer
220
(also sometimes referred to as a gate insulation layer) and a dummy electrode
232
are formed on a silicon substrate
210
. Next, the dummy electrode
232
is patterned. Then, a low concentration impurity diffusion layer
242
is formed in the silicon substrate
210
on the sides of the dummy electrode
232
. Next, an insulation layer (not shown) is formed over the entire surface, and the insulation layer and the gate dielectric layer
220
are etched by RIE (reactive ion etching) to form a sidewall spacer
250
on the side wall of the dummy electrode
232
. Then, a high concentration impurity diffusion layer
244
is formed in the silicon substrate
210
on the side of the sidewall spacer
250
.
Next, as shown in FIG.
9
(
b
), an insulation layer
260
is formed on the silicon substrate
210
, and the insulation layer
260
is then planarized to expose the dummy electrode
232
.
Next, as shown in FIG.
10
(
a
), the entire dummy electrode
232
is removed to form a through hole
270
.
Next, as shown in FIG.
10
(
b
), a metal layer is formed in a manner to fill the through hole
270
, and the metal layer is then etched-back to form a gate electrode
230
.
Techniques to form gate electrodes by a damascene method are described in several references such as U.S. Pat. No. 5,960,270, U.S. Pat. No. 5,391,510 and U.S. Pat. No. 5,434,093.
SUMMARY
Embodiments include to a method for manufacturing a semiconductor device, the method including the steps of: (a) forming a gate dielectric layer; (b) forming a first conduction layer having a specified pattern on the gate dielectric layer; (c) forming sidewall spacers on side walls of the first conduction layer; (d) depositing an insulation layer that covers the first conduction layer and the sidewall spacers; (e) planarizing the insulation layer until an upper surface of the first conduction layer is exposed; (f) removing a part of the first conduction layer in a manner so that the gate dielectric layer is not exposed, to thereby form a recessed section on the first conduction layer; and (g) filling a second conduction layer in the recessed section to form a gate electrode that includes at least the first conduction layer and the second conduction layer.
Embodiments also include a method for manufacturing a semiconductor device, the method including forming a gate dielectric layer on a substrate and forming a first conduction layer having a specified pattern on the gate dielectric layer. Sidewall spacers are formed on side walls of the first conduction layer. A part of the first conduction layer is removed in a manner so that the gate dielectric layer is not exposed, to thereby form a recessed section on the first conduction layer. A second conduction layer is provided in the recessed section to form a gate electrode that includes at least the first conduction layer and the second conduction layer.
Embodiments also include a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, sidewall spacers, a source region and a drain region. The gate electrode includes a first conduction layer and a second conduction layer. The first conduction layer is formed over the gate dielectric layer, and the second conduction layer is formed over the first conduction layer. The sidewall spacers are formed on side walls of the gate electrode. When the thickness of the first conduction layer is compared based on a top surface of the gate dielectric layer, the first conduction layer has thickness that gradually becomes greater from a central section thereof toward the side walls thereof.
Embodiments also include a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a gate electrode, sidewall spacers, a source region and a drain region. The gate electrode includes a first conduction layer and a second conduction layer. The first conduction layer is formed over the gate dielectric layer, and the second conduction layer is formed over the first conduction layer. The sidewall spacers are formed on side walls of the gate electrode. When the thickness of the first conduction layer is compared based on a top surface of the gate dielectric layer, an end portion of the first conduction layer has a greater thickness as compared to a thickness thereof at a central section thereof.


REFERENCES:
patent: 4786609 (1988-11-01), Chen
patent: 5306655 (1994-04-01), Kurimoto
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5405787 (1995-04-01), Kurimoto
patent: 5434093 (1995-07-01), Chau et al.
patent: 5721443 (1998-02-01), Wu
patent: 5879998 (1999-03-01), Krivokapic
patent: 5937299 (1999-08-01), Michael et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 5976934 (1999-11-01), Hayakawa
patent: 5986302 (1999-11-01), Fukatsu et al.
patent: 6087231 (2000-07-01), Xiang et al.
patent: 6228717 (2001-05-01), Hazama et al.
patent: 6271094 (2001-08-01), Boyd et al.
patent: 6348385 (2002-02-01), Cha et al.
patent: 6365459 (2002-04-01), Leu
patent: 6403997 (2002-06-01), Inumiya et al.
patent: 6465359 (2002-10-01), Yamada et al.
patent: 4-155932 (1992-05-01), None
U.S. application Ser. No. 09/963,924, filed Sep. 26, 2001, having U.S. patent Appl. Pub. No. US2002/0084498 A1, published on Jul. 4, 2002.
U.S. application Ser. No. 09/963,903, filed Sep. 26, 2001, having U.S. patent Appl. Pub. No. US2002/0117726 A1, published on Aug. 29, 2002.

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