Low thermal budget solution for PMD application using sacvd...

Details Low thermal budget solution for PMD application using sacvd... Low thermal budget solution for PMD application using sacvd...

2001-03-30

2004-03-09

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Utilizing reflow

C438S632000

Reexamination Certificate

active

06703321

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the formation of a borophosphosilicate glass (“BPSG”) layer during the fabrication of integrated circuits on semiconductor wafers. More particularly, the present invention relates to an improved reflow process that reduces the thermal budget of a fabrication process while providing gap-filling properties that enable the BPSG layer to meet the requirements of modern day manufacturing processes.
Silicon oxide is widely used as an insulating layer in the manufacture of semiconductor devices. A silicon oxide film can be deposited by thermal chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) processes from a reaction of silane (SiH
4
), tetraethoxysilane (Si(OC
2
H
5
)
4
), hereinafter referred to as “TEOS,” or a similar silicon-containing source, with an oxygen-containing source such as O
2
, ozone (O
3
), or the like.
One particular use for a silicon oxide film is as a separation layer between the polysilicon gate/interconnect layer and the first metal layer of MOS transistors. Such separation layers are referred to as premetal dielectric (PMD) layers because they are typically deposited before any of the metal layers in a multilevel metal structure. In addition to having a low dielectric constant, low stress and good adhesion properties, it is important for PMD layers to have good planarization and gap-fill characteristics.
When used as a PMD layer, the silicon oxide film is deposited over a silicon substrate having a lower level polysilicon gate/interconnect layer. The surface of the silicon substrate may include isolation structures, such as trenches, and raised or stepped surfaces, such as polysilicon gates and interconnects. The initially deposited film generally conforms to the topography of the substrate surface and is typically planarized or flattened before an overlying metal layer is deposited.
One method developed to fill the gaps and “planarize” or “flatten” the substrate surface involves forming a layer of relatively low-melting-point silicon oxide and then heating the substrate sufficiently to cause the layer to melt and flow as a liquid, resulting in a flat surface upon cooling. Such heating can be performed using either a rapid thermal pulse (RTP) method or conventional furnace, for example, and can be done in a dry (e.g., N
2
or O
2
) or wet (e.g., steam H
2
/O
2
) ambient. Each process has attributes that make that process desirable for a specific application.
Because of its low dielectric constant, low stress, good adhesion and gap-fill properties and relatively low reflow temperature, borophosphosilicate glass (“BPSG”) is one silicon oxide film that has found particular applicability in applications that employ a reflow step to planarize PMD layers. Standard BPSG films are formed by introducing a phosphorus-containing source and a boron-containing source into a processing chamber along with the silicon- and oxygen-containing sources normally required to form a silicon oxide layer.
As semiconductor design has advanced, the feature size of the semiconductor devices has dramatically decreased. Many integrated circuits (ICs) now have features, such as traces or trenches that are significantly less than a micron across. While the reduction in feature size has allowed higher device density, more chips per wafer, more complex circuits, lower operating power consumption, and lower cost, the smaller geometries have also given rise to new problems, or have resurrected problems that were once solved for larger geometries.
One manufacturing challenge presented by submicron devices is minimizing the overall thermal budget of the IC fabrication process in order to maintain shallow junctions and prevent the degradation of self-aligned titanium silicide contact structures, among other reasons. Hence, for at least this reason, it is desirable to provide methods of forming planarized insulating layers, such as BPSG layers, with lower thermal budget requirements.
SUMMARY OF THE INVENTION
The present invention provides exemplary methods, apparatus and systems for planarizing an insulating layer, such as a borophosphosilicate glass (BPSG) layer or an undoped silicate glass (USG) layer, deposited over a substrate.
In one embodiment, the method includes loading a substrate having a BPSG layer deposited thereover into a substrate processing chamber. In one embodiment, the BPSG layer is a premetal dielectric (PMD) layer, although the BPSG layer may be positioned elsewhere in the circuit device within the scope of the present invention. The BPSG layer has an upper surface that is generally non-planar. The substrate is exposed to an ultraviolet (UV) light at conditions sufficient to cause a reflow of the BPSG layer so that the upper surface is generally planar. The UV light is produced with a UV lamp, a laser, other provided UV light sources, and the like. In this manner, photonic energy is used instead of thermal energy to cause the insulating layer to reflow. The reflow fills the gaps, vias, trenches and the like, producing a generally planar surface.
In one embodiment, the UV light has a wavelength of about 150 nm±50 nm, although wavelengths throughout the UV spectrum may be used within the scope of the present invention. In alternative embodiments, the UV light has an energy level that is greater than about 10 electron volts (eV), and is about 15 eV.
The substrate, in one embodiment, is exposed to UV light for between about thirty (30) seconds and about fifteen (15) minutes. In another embodiment, the exposing step is maintained using UV light at an energy level that is at least about 10 eV, and for a duration that is at least about 30 seconds to produce sufficient reflow of the BPSG layer. In another embodiment, the UV light has a wavelength that is at least about 150 nm and the exposing step duration is at least about 30 seconds. It will be appreciated by those skilled in the art that the exposure time will depend, in part, on the UV light wavelength and/or energy, and the type and/or thickness of the insulating layer, among other things.
In one embodiment, the method includes maintaining a temperature in the substrate processing chamber between about 20 degrees Celsius and about 100 degrees Celsius during the exposing step. In this manner, a low thermal budget is used for the insulating layer reflow process.
In another embodiment, the exposing step exposes the substrate to UV light having a desired wavelength and a desired energy level to break at least some SiOH bonds in the BPSG layer. In this manner, the hydrogen content in the BPSG is reduced. Similarly, exposing the substrate to UV light helps densify the BPSG layer.
In another embodiment of the present invention, a method of forming a planarized insulating layer includes providing a substrate having a non-planar upper surface and depositing an insulating layer over the upper surface. The insulating layer has a generally non-planar upper surface, typically similar in contour to the substrate upper surface. The method includes exposing the insulating layer to a UV light at conditions sufficient to cause the insulating layer to reflow so that the insulating layer upper surface is generally planar. In one embodiment, the insulating layer comprises borophosphosilicate glass (BPSG), although other insulating layers, including other silicon oxide layers may be used within the scope of the present invention.
In one embodiment, the insulating layer is deposited by inserting the substrate into a substrate processing chamber and introducing a phosphorus-containing source and a boron-containing source into the processing chamber to deposit the BPSG insulating layer over the substrate. Examples of phosphorus-containing sources for use with the present invention include triethylphosphate (TEPO), triethylphosphite (TEP
i
), trimethylphosphate (TMOP), trimethylphosphite (TMP
i
), and similar compounds. Examples of boron-containing sources for use with the present invention include triethylborate (TEB), trimethylborate (TMB), and similar

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