Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-05-30
2004-01-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000
Reexamination Certificate
active
06680509
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to the fabrication of semiconductor devices and, more particularly, to the fabrication of the dielectric layers in semiconductor devices.
BACKGROUND OF THE INVENTION
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. During programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain.
A flash device that utilizes the ONO structure is a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type cell, such as the Mirror-Bit™ SONOS-type flash memory device available from Advanced Micro Devices, Sunnyvale, Calif. The SONOS type cell includes a bit-line, a word line and an ONO structure which function together to determine the location of the bit stored in memory. Important factors towards achieving high performance of the SONOS type cell include the quality and cleanliness of the ONO structure.
A problem exists with known SONOS fabrication techniques in that the quality and cleanliness of the ONO structure cannot be guaranteed during the fabrication process of the transistor. One reason that these factors cannot be guaranteed is that during production of the SONOS type cell, the top oxide layer of the ONO structure is subjected to repeated photoresist application and removal. For example, a resist layer is formed on the ONO structure to protect the device during arsenic implant that forms the underlying bit-line. After the arsenic is implanted, typically ashing (high temperature anneal or plasma treatment in an oxygen-containing atmosphere) and a wet clean are used to remove the resist layer.
Resist material remaining on the top oxide layer of the ONO structure can adversely affect the connection between the top oxide layer and an overlying polycrystalline silicon layer of the SONOS cell to degrade performance of the memory cell. To effectively remove the resist layer, the top oxide layer should be aggressively cleaned so that no organic residue of the resist material remains to contaminate the top oxide of the ONO structure. According to known SONOS type cell structures, however, if cleaning is accomplished with an aggressive acid, such as hydrofluoric acid, the aggressive acid or treatment can degrade the top oxide layer of the ONO structure.
Referring now to
FIGS. 1A-1D
, there is shown a conventional method of forming a bit-line by implantation of, e.g., arsenic (As). In
FIG. 1A
, a portion of a nascent SONOS structure
10
is shown. The nascent SONOS structure
10
includes a semiconductor substrate
12
, and an ONO structure
14
. The ONO structure
14
includes a bottom silicon oxide layer
16
, a silicon nitride layer
18
, and a top silicon oxide layer
20
.
As shown in
FIG. 1B
, next, a photoresist layer
22
is applied to the upper surface of the ONO structure
14
, and then a bit-line pattern is etched into the photoresist layer
22
.
As shown in
FIG. 1C
, As ions, shown schematically by arrows
24
, are implanted into the nascent SONOS structure
10
, to form implanted areas
26
in the ONO structure
14
and in the underlying semiconductor substrate
12
. The portion of the implanted area
26
which is in the semiconductor substrate
12
will form the bit-line structures in the completed SONOS structure
10
.
Following the As ion implantation step, the photoresist layer
22
is stripped, the upper oxide surface of the ONO structure
14
is cleaned, and the ONO structure
14
is consolidated by applying an oxidation cycle.
The stripping, cleaning and oxidation steps include the use of harsh chemicals which may etch the top silicon oxide layer
20
. In the portions of the top silicon oxide layer
20
through which As ions have been implanted, the implanted ions increase the susceptibility of the silicon oxide to erosion by such chemicals. As a result of the conventional stripping, oxidation and cleaning steps, a significant portion of the upper silicon oxide layer
20
may be etched away, as shown in FIG.
1
D.
FIG. 1D
shows a conventional SONOS structure
10
at the point in the fabrication process following As ion implantation to form bit-lines
28
, stripping of the photoresist, oxidation and cleaning, in which depressions or pits
30
have been formed in portions of the upper silicon oxide layer
20
. The portions of the upper silicon oxide layer
20
including the depressions or pits
30
have a reduced thickness compared to other portions of the upper silicon oxide layer
20
. This difference in thickness can have a significant negative impact on the operation and functioning of the memory cell to be formed in the SONOS structure
10
.
In sum, while there have been recent advances in EEPROM technology, numerous challenges exist in the fabrication of these devices. In particular, there is a need for an improved method of generating a SONOS type flash cell and EEPROM technology that allows for aggressive cleaning of the top layer of the ONO structure. In addition, a need remains for methods of fabricating a high quality ONO structure after multiple photoresist coating and cleaning cycles without degrading the top silicon oxide layer of the ONO structure.
SUMMARY OF THE INVENTION
The present invention addresses the challenges existing in fabrication of such SONOS type structures. The present invention meets the need for a method of fabricating a high quality ONO structure which can withstand the rigors of the fabrication process without degradation of the top silicon oxide layer of the ONO structure.
The present invention thus relates to a method for fabricating a SONOS device having a buried bit-line including the steps of: providing a semiconductor substrate having an ONO structure overlying the semiconductor substrate; forming a nitride barrier layer on the ONO structure to form a four-layer stack; forming a patterned photoresist layer on the nitride barrier layer; implanting ions through the four-layer stack to form a bit-line buried under the ONO structure; stripping the photoresist layer and cleaning an upper surface of the four-layer stack; and consolidating the four-layer stack by applying an oxidation cycle.
In one embodiment, the invention further relates to a SONOS-type device comprising an ONO structure comprising an top oxide layer having an upper surface; a nitride barrier layer formed on the upper surface, which thereby form a NONO four-layer stack; and a conductive layer formed on the nitride barrier layer. The conductive layer may be one of polysilicon, a silicide, or a metal. In one embodiment, the device has a SNONOS structure.
REFERENCES:
patent: 5418175 (1995-05-01), Hsue e
Lingunis Emmanuel H.
Ramsbey Mark
Sun Yu
Wu Yider
Yang Jean Yee-Mei
Advanced Micro Devices , Inc.
Flynn Nathan J.
Quinto Kevin
LandOfFree
Nitride barrier layer for protection of ONO structure from... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Nitride barrier layer for protection of ONO structure from..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Nitride barrier layer for protection of ONO structure from... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3225759